1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
Commit Graph

194250 Commits

Author SHA1 Message Date
Vedant Kumar
5db978be0e [LoopVectorize] Fix crash on "getNoopOrZeroExtend cannot truncate!" (PR45259)
In InnerLoopVectorizer::getOrCreateTripCount, when the backedge taken
count is a SCEV add expression, its type is defined by the type of the
last operand of the add expression.

In the test case from PR45259, this last operand happens to be a
pointer, which (according to llvm::Type) does not have a primitive size
in bits. In this case, LoopVectorize fails to truncate the SCEV and
crashes as a result.

Uing ScalarEvolution::getTypeSizeInBits makes the truncation work as expected.

https://bugs.llvm.org/show_bug.cgi?id=45259

Differential Revision: https://reviews.llvm.org/D76669
2020-03-30 10:14:14 -07:00
Yuanfang Chen
5676208119 [X86] make sure POP has implicit def/use of stack pointer when materializing 8-bit immediates for minsize
Summary:
Otherwise PostRA list scheduler may reorder instruction, such as

schedule this
'''
pushq  $0x8
pop    %rbx
lea    0x2a0(%rsp),%r15
'''
to
'''
pushq  $0x8
lea    0x2a0(%rsp),%r15
pop    %rbx
'''
by mistake. The patch is to prevent this to happen by making sure POP has
implicit use of SP.

Reviewers: craig.topper

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77031
2020-03-30 09:25:31 -07:00
Guillaume Chatelet
61ed715c3a [Alignment][NFC] Use Align version of getMachineMemOperand
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: jyknight, sdardis, nemanjai, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, jfb, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77059
2020-03-30 15:46:27 +00:00
Matt Arsenault
ee8a6b7a61 GlobalISel: Minor cleanups 2020-03-30 11:26:22 -04:00
Matt Arsenault
b4f2a15cb5 AMDGPU/GlobalISel: Hack to fix i24 argument lowering
I still think the call lowering type legalization logic split between
the generic code and target is too confusing, but largely induced by
the reliance on the DAG infrastructure.
2020-03-30 11:00:45 -04:00
Matt Arsenault
64e3cb670a AMDGPU/GlobalISel: Legalize 64-bit G_UDIV/G_UREM
Mostly ported from the DAG version. This results in much worse code
than the DAG version, largely due to a much worse expansion for
G_UMULH.
2020-03-30 10:57:37 -04:00
Chris Jackson
65cfb4a16b [DebugInfo] Ensure that a demanded bits optimisation in
InstCombine does not result in an incorrect debuginfo variable
value

- Add an additional salvage and a test.

Reviewers: aprantl, djtodoro

Differential Revision: https://reviews.llvm.org/D76854

Bugzilla:  https://bugs.llvm.org/show_bug.cgi?id=44371
2020-03-30 15:39:22 +01:00
Florian Hahn
18e00645a2 Revert "[Darwin] Respect -fno-unroll-loops during LTO."
As per post-commit comment at https://reviews.llvm.org/D76916, this
should better be done at the TU level.

This reverts commit 9ce198d6ed371399e9bd9ba8b48fbab0f4e60240.
2020-03-30 15:20:30 +01:00
Chris Jackson
2d8c535e77 [DebugInfo] Ensure dead store elimination can mark an operand
value as undefined

    - Correct a debug info salvage and add a test

    Reviewers: aprantl, vsk

    Differential Revision: https://reviews.llvm.org/D76930
    Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=45080
2020-03-30 14:58:14 +01:00
Sanjay Patel
c41823bb5a [InstCombine] add test for trunc-extelt; NFC
Goes with D76983
2020-03-30 09:43:03 -04:00
Guillaume Chatelet
f993ddbf7d [Alignment][NFC] Provide tightened up functions in SelectionDAG, MachineFunction and MachineMemOperand
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77046
2020-03-30 13:03:27 +00:00
Georgii Rymar
6e7e465fc6 [llvm-readobj] - Improve test of --elf-hash-histogram option.
This test missed the check of histograms printed for .hash sections.
It was removed by mistake in D71606 where I tried to get rid of precompiled objects
and did not realize that time that both SHT_GNU_HASH and SHT_HASH sections
were tested and not just GNU version.

Also it never tested aliases for the --elf-hash-histogram option.

Differential revision: https://reviews.llvm.org/D76920
2020-03-30 15:46:45 +03:00
Georgii Rymar
6e3c5fe844 [llvm-readobj][test] - Simplify hash-symbols test.
We are able to reduce `-DBITS=32/64` to reduce this test case.
I've rewrote the comments we had to generalize them and
fix wrong computations they contained.

Differential revision: https://reviews.llvm.org/D76924
2020-03-30 14:44:30 +03:00
Simon Pilgrim
2b1f75c079 [X86][AVX] lowerV4X128Shuffle - attempt to widen to 2x256 to simplify shuffles
If we are lowering to X86ISD::SHUF128 we are going to lose track of individual 128-bit lanes that are UNDEF, so if we can widen these to guarantee that they are sequential with their neighbour we should. This helps with later shuffle combines.
2020-03-30 12:22:26 +01:00
Florian Hahn
fcea358269 [Matrix] Rename emitChainedMatrixMultiply to emitMatrixMultiply (NFC).
The Chained in the name potentially leads to confusion. Also updated the
comment to drop the unnecessary mention of tile-sized.
2020-03-30 11:17:25 +01:00
Florian Hahn
fdeed10483 [AMDGPU] Drop const for value that is copied (NFC).
This fixes

    warning: loop variable 'Def' of type 'const llvm::Register' creates a copy from type 'const llvm::Register' [-Wrange-loop-analysis]

llvm::Register just contains a single unsigned and should be copied.

Reviewers: rampitec

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D77011
2020-03-30 10:59:59 +01:00
Florian Hahn
49b3d2c46a [CVP] Add additional icmp for ranges with undef to test. 2020-03-30 10:59:25 +01:00
Qiu Chaofan
de43cc4915 [NFC] [PowerPC] Update and add tests for ori
Use script to update test for ori with 32-bit imms, and add test for
ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
Sam Parker
a88c160cb1 [ARM][LowOverheadLoops] Add horizontal reduction support
Add a bit more logic into the 'FalseLaneZeros' tracking to enable
horizontal reductions and also make the VADDV variants
validForTailPredication.

Differential Revision: https://reviews.llvm.org/D76708
2020-03-30 09:55:41 +01:00
Guillaume Chatelet
d8275ca792 [Alignment][NFC] Return Align for SelectionDAGNodes::getOriginalAlignment/getAlignment
Summary:
Also deprecate getOriginalAlignment, getAlignment will take much more time as it is pervasive through the codebase (including TableGened files).

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76933
2020-03-30 07:26:48 +00:00
David Green
b1c13d77ac [ARM] MVE VMOV.i64
In the original batch of MVE VMOVimm code generation VMOV.i64 was left
out due to the way it was done downstream. It turns out that it's fairly
simple though. This adds the codegen for it, similar to NEON.

Bigendian is technically incorrect in this version, which John is fixing
in a Neon patch.
2020-03-30 07:44:23 +01:00
Craig Topper
2289b000f6 [TTI][X86] Fix the value passed to IsUnsigned for cost modeling of experimental.vector.reduce.smin/smax/umin/umax.
We were passing true for smax/smin and false for umax/umin.
2020-03-29 23:34:22 -07:00
Max Kazantsev
8794887cea [NFC] Remove obsolete checks followed by fix of isGuaranteedToTransferExecutionToSuccessor
In past, isGuaranteedToTransferExecutionToSuccessor contained some weird logic
for volatile loads/stores that was ultimately removed by patch D65375. It's time to
remove a piece of dependent logic that used to be a workaround for the code which
is now deleted.

Reviewed By: uenoku
Differential Revision: https://reviews.llvm.org/D76918
2020-03-30 12:24:41 +07:00
Juneyoung Lee
2cd7fcb259 [LangRef] Clarify the semantics of branch on undef
Summary:
This patch clarifies the semantics of branching on undef value.

Defining `br undef` as undefined behavior explains optimizations that use branch conditions, such as CVP (D76931) and GVN (propagateEquality).

For `switch cond`, it is defined to raise UB if cond is an expression containing undef && cond is not frozen &&
it may yield different values.
This allows that at the destination block the branch condition can be assumed to be frozen already (otherwise UB was already triggered).
This condition is slightly stricter than MemorySanitizer, which allows undef-y condition if it always leads to the same destination,
but it does not break MemorySanitizer because we are giving stricter constraint.

Reviewers: efriedma, fhahn, nikic, spatel, jdoerfert, nlopes

Reviewed By: nlopes

Subscribers: regehr, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76973
2020-03-30 11:41:47 +09:00
Jun Ma
1519f8d30a [Coroutines 2/2] Improve symmetric control transfer feature
Differential Revision: https://reviews.llvm.org/D76913
2020-03-30 09:53:09 +08:00
Jun Ma
9f7a51855e [Coroutines 1/2] Improve symmetric control transfer feature
Differential Revision: https://reviews.llvm.org/D76911
2020-03-30 09:53:09 +08:00
Craig Topper
8bfc3e764e [X86] Add sse4.1 RUNs lines to the min/max reduction cost model tests.
Mostly this matches the sse4.2 we already had command lines for.
Except in the i64 case since sse4.1 doesn't have pcmpgtq.
2020-03-29 16:05:35 -07:00
Daan Sprenkels
c80b7e3f8e [InstCombine] Add tests for trunc (extelt x); (NFC)
Baseline tests for D76983 (PR45314)

Differential Revision: https://reviews.llvm.org/D77024
2020-03-29 17:30:54 -04:00
Craig Topper
af68664485 [X86] Add sse4.2 command lines to min/max reduction tests.
SSE4.2 has the pcmpgtq instruction which we will use in
vXi64 reductions when its available.
2020-03-29 13:51:03 -07:00
David Green
fbea30d2df [ARM] VMOV.64 immediate tests. NFC 2020-03-29 21:08:43 +01:00
LLVM GN Syncbot
cf4881fd2f [gn build] Port 854f268ca62 2020-03-29 19:24:34 +00:00
Benjamin Kramer
4c79d49be9 [MC] Move deprecation infos from MCTargetDesc to MCInstrInfo
This allows emitting it only when the feature is used by a target.
Shrinks Release+Asserts clang by 900k.
2020-03-29 21:20:40 +02:00
Simon Pilgrim
5bc79f436c [X86][AVX] Combine 128/256-bit lane shuffles with zeroable upper subvectors to EXTRACT_SUBVECTOR (PR40720)
As explained on PR40720, EXTRACTF128 is always as good/better than VPERM2F128/SHUF128, and we can use the implicit zeroing of the uppers.
2020-03-29 19:51:38 +01:00
Simon Pilgrim
cf80897776 [X86] Add isAnyZero shuffle mask helper 2020-03-29 19:51:37 +01:00
Nikita Popov
6967b5c883 [InstCombine] Erase old mul when creating umulo
As we don't return the result of replaceInstUsesWith(), we are
responsible for erasing the instruction.

There is a small subtlety here in that we need to do this after
the other uses of Builder, which uses the original multiply as
the insertion point.

NFC apart from worklist order changes.
2020-03-29 20:46:08 +02:00
Nikita Popov
9434424736 [InstCombine] Use replaceOperand() in demanded elements simplification
To make sure that dead operands get DCEd. This fixes the largest
source of leftover dead operands we see in tests.

NFC apart from worklist changes.
2020-03-29 20:43:19 +02:00
Nikita Popov
98c2b02c04 [InstCombine] Use replaceOperand() in assoc cast simplification
To make sure the old operands are DCEd.

NFC apart from worklist order.
2020-03-29 20:28:37 +02:00
Nikita Popov
b667603246 [InstCombine] Erase old add when optimizing add overflow
We don't return the replaceInstUsesWith() result, so we're
responsible for cleaning up.

NFC apart from worklist order changes.
2020-03-29 20:20:14 +02:00
Uday Bondhugula
336d326470 Introduce support for lib function aligned_alloc in TLI / memory builtins
Aligned_alloc is a standard lib function and has been in glibc since
2.16 and in the C11 standard. It has semantics similar to malloc/calloc
for several analyses/transforms. This patch introduces aligned_alloc
in target library info and memory builtins. Subsequent ones will
make other passes aware and fix https://bugs.llvm.org/show_bug.cgi?id=44062

This change will also be useful to LLVM generators that need to allocate
buffers of vector elements larger than 16 bytes (for eg. 256-bit ones),
element boundary alignment for which is not typically provided by glibc malloc.

Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D76970
2020-03-29 23:36:24 +05:30
Matt Arsenault
d0c820ef49 GlobalISel: Add matcher for G_SHL 2020-03-29 14:03:07 -04:00
Matt Arsenault
88f2f59236 AMDGPU/GlobalISel: Remove redundant virtual 2020-03-29 14:03:07 -04:00
Matt Arsenault
f37e7222d1 AMDGPU: Fix using wrong instruction for FP conversion
This was was never actually hit, but FTRUNC was clearly not the intent
here.
2020-03-29 14:03:07 -04:00
Matt Arsenault
de61f4db43 AMDGPU: Add some additional tests for v_cvt_ubyte* formation
Use functions now that we have them for less boilerplate in the
output.
2020-03-29 14:03:07 -04:00
Matt Arsenault
8d9df1b07c AMDGPU: Fix typo 2020-03-29 14:03:06 -04:00
Sanjay Patel
c46bba2092 [VectorCombine] skip debug intrinsics first for efficiency 2020-03-29 13:58:04 -04:00
Sanjay Patel
d424ebe347 [InstCombine] make test independent of branch undef/UB; NFC 2020-03-29 13:32:47 -04:00
Simon Pilgrim
6bc7b2e92c [X86][AVX] Add tests for 512-bit shuffle patterns that could reduce to subvector extractions 2020-03-29 18:27:18 +01:00
Simon Pilgrim
a7ae4789c3 Remove unnecessary empty comments from test check lines. NFC. 2020-03-29 18:27:18 +01:00
Nikita Popov
365e061515 [InstCombine] Simplify select of cmpxchg transform
Rather than converting to a dummy select with equal true and false
ops, just directly return the resulting value.

As a side-effect, this fixes missing DCE of the previously replaced
operand.
2020-03-29 18:57:32 +02:00
Florian Hahn
d7782de60a [OpenMP] set_bits iterator yields unsigned elements, no reference (NFC).
BitVector::set_bits() returns an iterator range yielding unsinged
elements, which always will be copied while const & gives the impression
that there will be no copy. Newer version of clang complain:

    warning: loop variable 'SetBitsIt' is always a copy because the range of type 'iterator_range<llvm::BitVector::const_set_bits_iterator>' (aka 'iterator_range<const_set_bits_iterator_impl<llvm::BitVector> >') does not return a reference [-Wrange-loop-analysis]

Reviewers: jdoerfert, rnk

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D77010
2020-03-29 17:08:13 +01:00