allow, i.e. make a sequence of instructions to enable an indirect call using
jump-and-link and 2 temporary registers (which we save and ultimately restore).
Warning: if the delay slot of a function call is used to do meaningful work and
not just a NOP, this behavior is incorrect. However, the Sparc backend does not
yet utilize the delay slots effectively, so it is not necessary to make an
overly complicated algorithm for something that's not used.
llvm-svn: 7178
* FP double registers are now coded correctly
* Removed function which converted registers based on register types, it was
broken (because regTypes are broken)
llvm-svn: 7175
remembered in valuesStoredInFunction, but never traced at function return,
and that's too late to be finding the error anyway).
Stores trace both the value and the address being stored to,
but after some experience I think only values should be traced.
The pointer hash table just fills up far too quickly if every
store address were traced.
llvm-svn: 7169
out the entire llvm disassembly for the function at global constant-output
time, which caused the assembler to barf in 164.gzip. This fixes that
particular problem (though 164.gzip has other problems with X86 llc.)
llvm-svn: 7168
Fhourstones, McCat-vor, and many others...)
Printer.cpp: Print implicit uses for AddRegFrm instructions. Break gas
bug workarounds up into separate stanzas of code for each bug. Add new
workarounds for fild and fistp.
X86InstrInfo.def: Add O_ST0 implicit uses for more FP instrs where they
obviously apply. Also add PrintImplUses flags for FP instrs where they
are necessary for gas to understand the output.
llvm-svn: 7165
(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.
(2) Conditional move instructions must distinguish signed and unsigned
condition codes, e.g., MOVLE vs. MOVLEU.
(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
which produces a valid-looking instruction with bogus registers!
(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
add 2^k-1 before shifting, not add 1 after shifting. Sadly, these
are the same when k=0 so our poor test case worked fine.
(5) Casting between signed and unsigned values was not correct:
completely reimplemented.
(6) Zero-extension on unsigned values was bogus: I was only doing the
SRL and not the SLLX before it. Don't know WHAT I was thinking!
(7) And the most important class of changes: Sign-extensions on signed values.
Signed values are not sign-extended after ordinary operations,
so they must be sign-extended before the following cases:
-- passing to an external or unknown function
-- returning from a function
-- using as operand 2 of DIV or REM
-- using as either operand of condition-code setting operation
(currently only SUBCC), with smaller than 32-bit operands
Also, a couple of improvements:
(1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also.
(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
if the constant is 0. This was only being done for branch-on-SetCC-Const
when the branch is folded with the SetCC-Const.
llvm-svn: 7159
(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same
register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
llvm-svn: 7152
(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
llvm-svn: 7151
correct: empirically, "regType" is wrong for a number of registers. Thus, one
can only rely on the "regClass" to figure out what kind of register one is
dealing with.
This change switches to using only "regClass" and adds a few extra DEBUG() print
statements and a few clean-ups in comments and code, mostly minor.
llvm-svn: 7103
the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
actually assigned into the right portion of the instruction.
llvm-svn: 7074
* Setting ENABLE_X86_JIT or ENABLE_SPARC_JIT on the `make' command-line will
force the inclusion of that JIT on a different architecture
* If neither JIT is enabled (e.g., compiling on a different architecture), the
-march option will not be available to LLI.
* As a side effect of the $ARCH variable, the Sparc LLI can now link just a bit
faster by not including the x86 library.
llvm-svn: 7070
area to avoid using up precious stack space within the 4095 offset limit
from %fp. Such objects that would themselves live at a large offset
were being put there already so this is a simple change.
llvm-svn: 7066
