Che-Liang Chiou
962612fc5c
ptx: add basic support of predicate execution
...
llvm-svn: 127569
2011-03-13 17:26:00 +00:00
Eric Christopher
80a45901e0
Sometimes isPredicable lies to us and tells us we don't need the operands.
...
Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
llvm-svn: 127518
2011-03-12 01:09:29 +00:00
Jim Grosbach
f7531e7697
Add FIXME.
...
llvm-svn: 127516
2011-03-12 00:51:00 +00:00
Jim Grosbach
555d910477
Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
...
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.
llvm-svn: 127515
2011-03-12 00:45:26 +00:00
Jim Grosbach
923c731f15
Add a FIXME.
...
llvm-svn: 127511
2011-03-11 23:25:21 +00:00
Jim Grosbach
daffeb06fb
Pseudo-ize the ARM 'B' instruction.
...
llvm-svn: 127510
2011-03-11 23:24:15 +00:00
Jim Grosbach
2226dfbea2
Remove dead code. These ARM instruction definitions no longer exist.
...
llvm-svn: 127509
2011-03-11 23:15:02 +00:00
Jim Grosbach
009af69d6d
Pseudo-ize VMOVDcc and VMOVScc.
...
llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Jim Grosbach
61ff87cd2d
80 columns
...
llvm-svn: 127505
2011-03-11 23:00:16 +00:00
Jim Grosbach
27eaca3e0d
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
...
effect that we get proper instruction printing using the "pop" mnemonic for it.
llvm-svn: 127502
2011-03-11 22:51:41 +00:00
Jim Grosbach
ee6075cda5
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
...
as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
Jim Grosbach
3329263352
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
...
and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
...
as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
Jim Grosbach
fff6ff502b
This FIXME has been fixed.
...
llvm-svn: 127483
2011-03-11 20:07:37 +00:00
Jim Grosbach
2ecded3a94
Properly pseudo-ize ARM MVNCCi.
...
llvm-svn: 127482
2011-03-11 19:55:55 +00:00
Jim Grosbach
39804c0b44
Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).
...
llvm-svn: 127469
2011-03-11 18:00:42 +00:00
Chris Lattner
2cd24b852f
silence a conditional assignment -Wuninitialized warning.
...
llvm-svn: 127453
2011-03-11 02:12:51 +00:00
Jim Grosbach
ed45ac390c
Properly pseudo-ize ARM MOVCCi and MOVCCi16.
...
llvm-svn: 127442
2011-03-11 01:09:28 +00:00
Eric Christopher
46f43c9cce
Change the x86 32-bit scheduler to register pressure and fix up the
...
corresponding testcases back to the previous versions.
Fixes some performance regressions only seen on 32-bit.
llvm-svn: 127441
2011-03-11 01:05:58 +00:00
Jim Grosbach
1986d9ac8f
Properly pseudo-ize MOVCCr and MOVCCs.
...
llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Jim Grosbach
5891b1323a
DMB can just be a pat referencing MCR.
...
llvm-svn: 127423
2011-03-10 19:27:17 +00:00
Jim Grosbach
4b74ef6ca9
Reorganize a bit. No functional change, just moving patterns up.
...
llvm-svn: 127422
2011-03-10 19:21:08 +00:00
Jim Grosbach
db549a7f6c
Pseudo-instructions are codegenonly by definition.
...
llvm-svn: 127420
2011-03-10 19:06:39 +00:00
Justin Holewinski
a26d2f782e
PTX: Add preliminary support for floating-point divide and multiply-and-add
...
llvm-svn: 127410
2011-03-10 16:57:18 +00:00
Che-Liang Chiou
fc6c7ba9d5
ptx: add the rest of special registers of ISA version 2.0
...
llvm-svn: 127397
2011-03-10 04:05:57 +00:00
Stuart Hastings
fd42046d56
Revert 127359; it broke lencod.
...
llvm-svn: 127382
2011-03-10 00:25:53 +00:00
Evan Cheng
a3a7a7e364
Re-commit 127368 and 127371. They are exonerated.
...
llvm-svn: 127380
2011-03-10 00:16:32 +00:00
Evan Cheng
d7a2008a55
Revert 127368 and 127371 for now.
...
llvm-svn: 127376
2011-03-09 23:53:17 +00:00
Evan Cheng
b717770dfe
Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more
...
flexible.
If it returns a register class that's different from the input, then that's the
register class used for cross-register class copies.
If it returns a register class that's the same as the input, then no cross-
register class copies are needed (normal copies would do).
If it returns null, then it's not at all possible to copy registers of the
specified register class.
llvm-svn: 127368
2011-03-09 22:47:38 +00:00
Benjamin Kramer
f1c1220d8f
Fix a pasto that broke all x86_64-elf targets.
...
llvm-svn: 127365
2011-03-09 22:07:13 +00:00
Stuart Hastings
61f9a3dab2
X86 byval copies no longer always_inline. <rdar://problem/8706628>
...
llvm-svn: 127359
2011-03-09 21:10:30 +00:00
Johnny Chen
6bf5d7a170
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
...
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
llvm-svn: 127354
2011-03-09 20:01:14 +00:00
Bruno Cardoso Lopes
88bef593d8
Improve varags handling, with testcases. Patch by Sasa Stankovic
...
llvm-svn: 127349
2011-03-09 19:22:22 +00:00
Jan Sjödin
c7c66d9f88
Add createELFObjectTargetWriter method to TargetAsmBackend, which enables construction of non-standard ELFObjectWriters that can be used in MCJIT.
...
llvm-svn: 127346
2011-03-09 18:44:41 +00:00
NAKAMURA Takumi
fe84f8672a
Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4.
...
llvm-svn: 127328
2011-03-09 11:33:15 +00:00
Bill Wendling
68934338ab
* Correct encoding for VSRI.
...
* Add tests for VSRI and VSLI.
llvm-svn: 127297
2011-03-09 00:33:17 +00:00
Bill Wendling
b790c462c0
Correct the encoding for VRSRA and VSRA instructions.
...
llvm-svn: 127294
2011-03-09 00:00:35 +00:00
Bill Wendling
ab9f04b6d8
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
...
* Update the NEON shift instruction test to expect what 'as' produces.
llvm-svn: 127293
2011-03-08 23:48:09 +00:00
Benjamin Kramer
d5782492c8
X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1.
...
Found by inspection.
llvm-svn: 127247
2011-03-08 15:20:20 +00:00
Justin Holewinski
d7426856e9
PTX: Add intrinsic support for ntid, ctaid, and nctaid registers
...
llvm-svn: 127246
2011-03-08 14:10:18 +00:00
Eric Christopher
72d7cc25f3
Turn on list-ilp scheduling by default on x86 and x86-64, fix up
...
testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.
Performance results:
roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated
john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES
Small compile time impact.
llvm-svn: 127208
2011-03-08 02:42:25 +00:00
Bob Wilson
f8c4d1ded9
Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.
...
llvm-svn: 127198
2011-03-08 01:17:20 +00:00
Bob Wilson
94403e6221
Fix comment typos.
...
llvm-svn: 127197
2011-03-08 01:17:16 +00:00
Bill Wendling
958e854f40
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
...
expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
Cameron Zwarich
a1920d7f51
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
...
llvm-svn: 127175
2011-03-07 21:56:36 +00:00
Anton Korobeynikov
8c7010e832
ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case
...
llvm-svn: 127106
2011-03-05 18:44:00 +00:00
Anton Korobeynikov
f15e269356
In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.
...
llvm-svn: 127105
2011-03-05 18:43:55 +00:00
Anton Korobeynikov
d8873d31a8
Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
...
llvm-svn: 127104
2011-03-05 18:43:50 +00:00
Anton Korobeynikov
d4828b54ec
Add unwind information emission for thumb stuff
...
llvm-svn: 127103
2011-03-05 18:43:43 +00:00
Anton Korobeynikov
7ba97c2831
Handle MI flags inside Thumb2SizeReduction pass.
...
llvm-svn: 127102
2011-03-05 18:43:38 +00:00