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13 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
dad0022424 Also expand 64-bit bitcasts. 
llvm-svn: 182229
 2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen
e033165fd4 Implement spill and fill of I64Regs. 
llvm-svn: 182228
 2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen
f777e6d131 Mark i64 SETCC as expand so it is turned into a SELECT_CC. 
llvm-svn: 182227
 2013-05-20 00:28:36 +00:00
Jakob Stoklund Olesen
50d419ac93 Don't use %g0 to materialize 0 directly. 
The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

llvm-svn: 182225
 2013-05-19 21:47:13 +00:00
Jakob Stoklund Olesen
702a7c68c9 Handle i64 FrameIndex nodes in SPARC v9 mode. 
llvm-svn: 182216
 2013-05-19 19:14:24 +00:00
Jakob Stoklund Olesen
d8a2b84611 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985
 2013-04-21 21:18:03 +00:00
Jakob Stoklund Olesen
b4edc00933 Add 64-bit multiply and divide instructions for SPARC v9. 
llvm-svn: 179582
 2013-04-16 02:57:02 +00:00
Jakob Stoklund Olesen
3b790b7f2e Use i32 for all SPARC shift amounts, even in 64-bit mode. 
Test case by llvm-stress.

llvm-svn: 179477
 2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen
8a184a7fe4 Add 64-bit load and store instructions. 
There is only a few new instructions, the rest is handled with patterns.

llvm-svn: 178528
 2013-04-02 04:09:28 +00:00
Jakob Stoklund Olesen
22fe26207f Basic 64-bit ALU operations. 
SPARC v9 extends all ALU instructions to 64 bits, so we simply need to
add patterns to use them for both i32 and i64 values.

llvm-svn: 178527
 2013-04-02 04:09:23 +00:00
Jakob Stoklund Olesen
d57f9ab92f Materialize 64-bit immediates. 
The last resort pattern produces 6 instructions, and there are still
opportunities for materializing some immediates in fewer instructions.

llvm-svn: 178526
 2013-04-02 04:09:17 +00:00
Jakob Stoklund Olesen
5ef2195726 Add 64-bit shift instructions. 
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.

This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.

llvm-svn: 178525
 2013-04-02 04:09:12 +00:00
Jakob Stoklund Olesen
9fbfce2d11 Add support for 64-bit calling convention. 
This is far from complete, but it is enough to make it possible to write
test cases using i64 arguments.

Missing features:
- Floating point arguments.
- Receiving arguments on the stack.
- Calls.

llvm-svn: 178523
 2013-04-02 04:09:02 +00:00