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42 Commits

Author SHA1 Message Date
Evan Cheng
e46afad99b Avoid breaking vstd when reg_sequence is not used. 
llvm-svn: 103513
 2010-05-11 21:07:36 +00:00
Evan Cheng
5311f25b0b Model some vst3 and vst4 with reg_sequence. 
llvm-svn: 103453
 2010-05-11 01:19:40 +00:00
Evan Cheng
91747dc5dc Model some vld3 instructions with REG_SEQUENCE. 
llvm-svn: 103437
 2010-05-10 21:26:24 +00:00
Evan Cheng
7f0d8f1ab0 Model vld2 / vst2 with reg_sequence. 
llvm-svn: 103411
 2010-05-10 17:34:18 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.

llvm-svn: 103194
 2010-05-06 20:33:48 +00:00
Evan Cheng
cfe5f2dba5 Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. 
llvm-svn: 103124
 2010-05-05 22:15:40 +00:00
Evan Cheng
85d27d4ab2 Do not pre-allocate for registers which form a REG_SEQUENCE. 
llvm-svn: 103041
 2010-05-04 20:38:12 +00:00
Bob Wilson
58c4740582 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
 2010-03-23 06:20:33 +00:00
Bob Wilson
2764399dd8 Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
 2010-03-23 05:25:43 +00:00
Bob Wilson
f23a45e151 Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
 2010-03-22 18:13:18 +00:00
Bob Wilson
73d7323c91 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
 2010-03-20 22:13:40 +00:00
Bob Wilson
a98f30a3a2 Rename some instructions for consistency and sanity: use "_UPD" suffix for 
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066
 2010-03-20 18:35:24 +00:00
Bob Wilson
3778e7f389 Revert 98683. It is breaking something in the disassembler. 
llvm-svn: 98692
 2010-03-16 23:01:13 +00:00
Bob Wilson
79f10e6233 Remove redundant writeback flag from ARM address mode 6. Also remove the 
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.

llvm-svn: 98683
 2010-03-16 21:44:40 +00:00
Chris Lattner
9ce833945e improve portability to avoid conflicting with std::next in c++'0x. 
Patch by Howard Hinnant!

llvm-svn: 90365
 2009-12-03 00:50:42 +00:00
Jim Grosbach
73c1e315e1 Support alignment specifier for NEON vld/vst instructions 
llvm-svn: 86404
 2009-11-07 21:25:39 +00:00
Nick Lewycky
711c726c97 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
 2009-10-25 06:33:48 +00:00
Bob Wilson
8092fef09a Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson
979cb24a81 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson
276bdabb9a Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83526
 2009-10-08 05:18:18 +00:00
Bob Wilson
8aa1d328b5 Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Bob Wilson
729cd181a2 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson
3cbf156518 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Bob Wilson
0ffa9679a5 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Bob Wilson
cee91108da Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Bob Wilson
62a3e55cea Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Bob Wilson
9bb47b3e5d Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Bob Wilson
b38401ccef Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson
8cd1ea81c4 Add codegen support for NEON vld2 operations on quad registers. 
llvm-svn: 83422
 2009-10-06 22:01:59 +00:00
Bob Wilson
8c108dc476 Use copyRegToReg hook to copy registers. 
llvm-svn: 83421
 2009-10-06 22:01:15 +00:00
Bob Wilson
6972a16bbc Add support for generating code for vst{234}lane intrinsics. 
llvm-svn: 80707
 2009-09-01 18:51:56 +00:00
Bob Wilson
bebadd11e4 Generate code for vld{234}_lane intrinsics. 
llvm-svn: 80656
 2009-09-01 04:26:28 +00:00
Bob Wilson
0cf2be2466 Generate Neon VTBL and VTBX instructions from the corresponding intrinsics. 
llvm-svn: 78835
 2009-08-12 20:51:55 +00:00
Bob Wilson
bd7627b23e Implement Neon VST[234] operations. 
llvm-svn: 78330
 2009-08-06 18:47:44 +00:00
Bob Wilson
905678ab37 Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.

llvm-svn: 78263
 2009-08-06 00:24:27 +00:00
Bob Wilson
6ee52e0047 Add a new pre-allocation pass to assign adjacent registers for Neon instructions 
that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.

llvm-svn: 78256
 2009-08-05 23:12:45 +00:00