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Commit Graph

16 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
5c74e232b1 [Hexagon] Validate register class when doing bit simplification
llvm-svn: 277740
2016-08-04 17:56:19 +00:00
Krzysztof Parzyszek
0ae2c174f5 [Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors
llvm-svn: 277626
2016-08-03 18:35:48 +00:00
Krzysztof Parzyszek
79d02725d4 [Hexagon] Recognize vcombine in copy propagation
llvm-svn: 277528
2016-08-02 21:49:20 +00:00
Davide Italiano
f7847d4aa2 [HexagonBitSimplify] Remove dead code.
llvm-svn: 277284
2016-07-30 22:07:18 +00:00
Krzysztof Parzyszek
0984ca425e [Hexagon] Gracefully handle reg class mismatch in HexagonLoopReschedule
llvm-svn: 276793
2016-07-26 19:17:13 +00:00
Krzysztof Parzyszek
97d3aa900c [Hexagon] Rerun bit tracker on new instructions in RIE
Consider this case:
  vreg1 = A2_zxth vreg0   (1)
  ...
  vreg2 = A2_zxth vreg1   (2)

Redundant instruction elimination could delete the instruction (1)
because the user (2) only cares about the low 16 bits. Then it could
delete (2) because the input is already zero-extended. The problem
is that the properties allowing each individual instruction to be
deleted depend on the existence of the other instruction, so either
one can be deleted, but not both.
The existing check for this situation in RIE was insufficient. The
fix is to update all dependent cells when an instruction is removed
(replaced via COPY) in RIE.

llvm-svn: 276792
2016-07-26 19:08:45 +00:00
Krzysztof Parzyszek
6d72583592 [Hexagon] Bitwise operations for insert/extract word not simplified
Change the bit simplifier to generate REG_SEQUENCE instructions in
addition to COPY, which will handle cases of word insert/extract.

llvm-svn: 276787
2016-07-26 18:30:11 +00:00
Duncan P. N. Exon Smith
90f39bd353 Hexagon: Avoid implicit iterator conversions, NFC
Avoid implicit iterator conversions from MachineInstrBundleIterator to
MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr&
over MachineInstr* and switching to range-based for loops.

There's a long tail of API cleanup here, but I'm planning to leave the
rest to the Hexagon maintainers.  HexagonInstrInfo defines many of its
own predicates, and most of them still take MachineInstr*.  Some of
those actually check for nullptr, so I didn't feel comfortable changing
them to MachineInstr& en masse.

llvm-svn: 275142
2016-07-12 01:55:32 +00:00
Rafael Espindola
b8700788a8 Delete more dead code.
Found by gcc 6.

llvm-svn: 273322
2016-06-21 21:51:41 +00:00
Benjamin Kramer
5699dda316 Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.
No functionality change intended.

llvm-svn: 272516
2016-06-12 17:30:47 +00:00
Andrew Kaylor
927565d9fa Add optimization bisect opt-in calls for Hexagon passes
Differential Revision: http://reviews.llvm.org/D19509

llvm-svn: 267593
2016-04-26 19:46:28 +00:00
Mehdi Amini
9ff867f98c [NFC] Header cleanup
Removed some unused headers, replaced some headers with forward class declarations.

Found using simple scripts like this one:
clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap'

Patch by Eugene Kosov <claprix@yandex.ru>

Differential Revision: http://reviews.llvm.org/D19219

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 266595
2016-04-18 09:17:29 +00:00
Krzysztof Parzyszek
bccfe64a1e [Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword
llvm-svn: 257815
2016-01-14 21:59:22 +00:00
Krzysztof Parzyszek
d9129a3d14 [Hexagon] Handle HVX registers in bit simplification
llvm-svn: 257811
2016-01-14 21:45:43 +00:00
Krzysztof Parzyszek
d9323342be [Hexagon] Do not insert non-phis before phis in bit simplification
llvm-svn: 257606
2016-01-13 15:48:18 +00:00
Krzysztof Parzyszek
4625bb8dfb [Hexagon] Bit-based instruction simplification
Analyze bit patterns of operands and values of instructions to perform
various simplifications, dead/redundant code elimination, etc.

llvm-svn: 250868
2015-10-20 22:57:13 +00:00