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Commit Graph

15 Commits

Author SHA1 Message Date
Chris Lattner
da05d37aa1 Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
hasImplicitDefOfPhysReg methods.  Use them to remove a 
look in X86 fast isel.

llvm-svn: 68886
2009-04-12 07:26:51 +00:00
Bob Wilson
c53238dff1 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714
2009-04-09 17:16:43 +00:00
Evan Cheng
15495e1cfe Clarify comments.
llvm-svn: 63851
2009-02-05 08:41:53 +00:00
Dan Gohman
8271066844 Tidy up #includes, deleting a bunch of unnecessary #includes.
llvm-svn: 61715
2009-01-05 17:59:02 +00:00
Dan Gohman
cfc84d4332 Clarify a comment.
llvm-svn: 61338
2008-12-22 19:44:39 +00:00
Dan Gohman
5dad0993a9 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
llvm-svn: 60487
2008-12-03 18:15:48 +00:00
Dan Gohman
ac6561793c Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's
foldMemoryOperand how to "fold" them, by converting them into constant-pool
loads. When they aren't folded, they use xorps/cmpeqd, but for example when
register pressure is high, they may now be folded as memory operands, which
reduces register pressure.

Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will
remat it instead of copying zeros around (V_SETALLONES was already marked).

llvm-svn: 60461
2008-12-03 05:21:24 +00:00
Evan Cheng
e7afdb2a42 Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.
TableGen has been taught to generate the lists from instruction definitions.

llvm-svn: 57722
2008-10-17 21:00:09 +00:00
Bill Wendling
b56bc61cf4 Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.

llvm-svn: 51660
2008-05-28 22:54:52 +00:00
Dan Gohman
b05ea92f80 Fix some minor errors in comments.
llvm-svn: 49445
2008-04-09 20:08:06 +00:00
Evan Cheng
9af68f56c5 Remove isImplicitDef TargetInstrDesc flag.
llvm-svn: 48381
2008-03-15 00:19:36 +00:00
Evan Cheng
c7ef6dc2db Remove an invalid assertion now that there are implicit virtual register operands.
llvm-svn: 47493
2008-02-22 19:25:04 +00:00
Chris Lattner
bfffa4f21e Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad. 

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags.  Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.

llvm-svn: 45843
2008-01-10 23:08:24 +00:00
Chris Lattner
9b7b3ade8f add a mayLoad property for machine instructions, a correlary to mayStore.
This is currently not set by anything.

llvm-svn: 45748
2008-01-08 18:05:21 +00:00
Chris Lattner
ba567fa77b split TargetInstrDesc out into its own header file.
llvm-svn: 45696
2008-01-07 07:33:08 +00:00