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Author SHA1 Message Date
Dale Johannesen
0124a7db51 Testcases for ppc atomics. 
llvm-svn: 55556
 2008-08-30 00:54:31 +00:00
Owen Anderson
6c8f04643e Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg 
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.

llvm-svn: 55555
 2008-08-30 00:38:46 +00:00
Dale Johannesen
1cfbb25e75 Add ppc partial-word ATOMIC_CMP_SWAP. 
llvm-svn: 55554
 2008-08-30 00:08:53 +00:00
Evan Cheng
c1c53221c5 Swap fp comparison operands and change predicate to allow load folding (safely this time). 
llvm-svn: 55553
 2008-08-29 23:22:12 +00:00
Evan Cheng
a884330e08 Use static_cast instead of C style cast. 
llvm-svn: 55552
 2008-08-29 23:21:31 +00:00
Evan Cheng
9ee227f1df Fix 80 col. violations. 
llvm-svn: 55551
 2008-08-29 23:20:46 +00:00
Evan Cheng
79d2a8f97d xfail this. 
llvm-svn: 55550
 2008-08-29 22:59:13 +00:00
Evan Cheng
2a3e05b519 Back out 55498. It broken Apple style bootstrapping. 
llvm-svn: 55549
 2008-08-29 22:21:44 +00:00
Evan Cheng
17382f9ffb Backing out 55521. Not safe. 
llvm-svn: 55548
 2008-08-29 22:13:21 +00:00
Dale Johannesen
bc977ce106 Add partial word version of ATOMIC_SWAP. 
llvm-svn: 55546
 2008-08-29 18:29:46 +00:00
Owen Anderson
3aa3841da2 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
llvm-svn: 55545
 2008-08-29 17:45:56 +00:00
Chris Lattner
a90998343b regenerate 
llvm-svn: 55542
 2008-08-29 17:20:18 +00:00
Chris Lattner
efbbbb0cde Asmprint nameless instructions as: 
%4 = add ...

instead of:

add ...    ; 4

This makes opt -print-cfg output actually usable and makes .ll files
generally easier to read.  This fixes PR2480

llvm-svn: 55541
 2008-08-29 17:19:30 +00:00
Chris Lattner
f24550c9d2 allow this to pass. 
llvm-svn: 55540
 2008-08-29 17:18:26 +00:00
Chris Lattner
b23f7dae39 Add support for parsing .ll files that have numbers in front of 
nameless values, such as:

%3 = add i32 4, 2

This fixes the first half of PR2480

llvm-svn: 55539
 2008-08-29 17:12:13 +00:00
Evan Cheng
3fb02ae0b6 TableGen'ing instruction encodings. 
llvm-svn: 55533
 2008-08-29 07:42:03 +00:00
Evan Cheng
b38decd917 addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode. 
llvm-svn: 55531
 2008-08-29 07:40:52 +00:00
Evan Cheng
5150e3da45 MVN is addrmode1. 
llvm-svn: 55530
 2008-08-29 07:36:24 +00:00
Daniel Dunbar
8a2cc13fb3 Add GlobalValue::{removeFromParent,eraseFromParent} 
llvm-svn: 55529
 2008-08-29 07:30:15 +00:00
Evan Cheng
f90bc9a050 More refactoring. 
llvm-svn: 55528
 2008-08-29 06:41:12 +00:00
Daniel Dunbar
1b3e44db87 Add DenseMap::lookup: 
/// lookup - Return the entry for the specified key, or a default
  /// constructed value if no such entry exists.

llvm-svn: 55523
 2008-08-29 00:48:44 +00:00
Evan Cheng
cdd06ba3f4 Swap fp comparison operands and change predicate to allow load folding. 
llvm-svn: 55521
 2008-08-28 23:48:31 +00:00
Evan Cheng
c50df85672 Refactor ARM instruction format definitions into a separate file. No functionality changes. 
llvm-svn: 55518
 2008-08-28 23:39:26 +00:00
Dan Gohman
c7b8401b77 Add a target callback for FastISel. 
llvm-svn: 55512
 2008-08-28 23:21:34 +00:00
Gabor Greif
5ec5f19852 remove tabs, fix > 80 cols 
llvm-svn: 55511
 2008-08-28 23:19:51 +00:00
Bill Wendling
96d5d65b1d Add another description to my entry. 
llvm-svn: 55510
 2008-08-28 23:16:37 +00:00
Gabor Greif
de8ed9f431 just a brain dump for a small tool 
that brings us to 80-col violations
or tabs.

Usage:
  visit-violations <file>

At the moment it outputs editor invocations.

llvm-svn: 55509
 2008-08-28 23:15:28 +00:00
Chris Lattner
673f4ce5f7 rename destroy -> releaseMemory to properly hook into passmgr. 
llvm-svn: 55508
 2008-08-28 22:56:53 +00:00
Nicolas Geoffray
05014c43fa Add support for JIT exceptions on Darwin. Since we're dealing with libgcc, 
whose darwin code was written after the ability to dynamically register frames,
we need to do special hacks to make things work.

llvm-svn: 55507
 2008-08-28 22:34:49 +00:00
Gabor Greif
c3711501ef fix the output dumbness I have introduced some time ago 
llvm-svn: 55506
 2008-08-28 22:32:39 +00:00
Gabor Greif
86c795a8ca erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics 
llvm-svn: 55504
 2008-08-28 21:40:38 +00:00
Dan Gohman
481731693d Implement null and undef values for FastISel. 
llvm-svn: 55500
 2008-08-28 21:19:07 +00:00
Mon P Wang
7566974359 In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN 
llvm-svn: 55499
 2008-08-28 21:04:05 +00:00
Dan Gohman
35a69c106a Optimize DAGCombiner's worklist processing. Previously it started 
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

llvm-svn: 55498
 2008-08-28 21:01:56 +00:00
Dan Gohman
9a6f5b0bdd Move CaseBlock, JumpTable, and BitTestBlock to be members of 
SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.

llvm-svn: 55497
 2008-08-28 20:38:18 +00:00
Dan Gohman
f8e43fa400 Fix a FastISel bug where the instructions from lowering the arguments 
were being emitted after the first instructions of the entry block.

llvm-svn: 55496
 2008-08-28 20:28:56 +00:00
Rafael Espindola
1cd4fc3111 Use resize instead of reserve. Reserve doesn't change size(). 
llvm-svn: 55486
 2008-08-28 18:32:53 +00:00
Rafael Espindola
31c516aabe Reduce the size of the Parts vector. 
llvm-svn: 55483
 2008-08-28 18:29:58 +00:00
Owen Anderson
675ace60a1 Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG. 
llvm-svn: 55482
 2008-08-28 18:26:01 +00:00
Owen Anderson
a5b87bf7e2 Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling. 
llvm-svn: 55480
 2008-08-28 18:06:12 +00:00
Dale Johannesen
e9a1266213 Implement partial-word binary atomics on ppc. 
llvm-svn: 55478
 2008-08-28 17:53:09 +00:00
Owen Anderson
8c991b6f8a FastEmitInst_extractsubreg doesn't need to be passed the register class. It can get it from MachineRegisterInfo instead. 
llvm-svn: 55476
 2008-08-28 17:47:37 +00:00
Dan Gohman
8f4d612996 Revert r55467; it causes regressions in UnitTests/Vector/divides, 
Benchmarks/sim/sim, and others on x86-64.

llvm-svn: 55475
 2008-08-28 17:22:54 +00:00
Rafael Espindola
17b967216a Correctly resize the Parts array. 
llvm-svn: 55471
 2008-08-28 14:24:45 +00:00
Evan Cheng
28b0b18082 If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy. 
llvm-svn: 55467
 2008-08-28 07:53:51 +00:00
Evan Cheng
419506a149 FsFLD0S{S|D} and V_SETALLONES are as cheap as moves. 
llvm-svn: 55466
 2008-08-28 07:52:25 +00:00
Chris Lattner
bd43eec286 Make the verifier reject instructions which have null pointers 
for operands: rdar://6179606.  no testcase, because I can't write
a .ll file that is this broken ;-)

llvm-svn: 55460
 2008-08-28 04:02:44 +00:00
Chris Lattner
460b89cb3a Clear the intervals list in "destroy", patch by 
Prakash Prabhu!

llvm-svn: 55458
 2008-08-28 03:33:03 +00:00
Dale Johannesen
490c016734 Split the ATOMIC NodeType's to include the size, e.g. 
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457
 2008-08-28 02:44:49 +00:00
Dale Johannesen
ae522b8463 This test crashes on non-x86 host; make SSE explicit. 
Feel free to fix a better way!

llvm-svn: 55456
 2008-08-28 01:51:09 +00:00