RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
Code Issues Projects Releases Wiki Activity
60,904 Commits 4 Branches 5 Tags 704 MiB
5ec2a338ac
Commit Graph

60904 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jim Grosbach
523fa7acaa Fix the post-RA instruction scheduler to handle instructions referenced by 
more than one dbg_value instruction. rdar://7759363

llvm-svn: 104174
 2010-05-19 22:57:06 +00:00
Evan Cheng
9fe8c861bf Code clean up. 
llvm-svn: 104173
 2010-05-19 22:42:23 +00:00
Devang Patel
069568c287 Revert r104165. 
llvm-svn: 104172
 2010-05-19 21:58:28 +00:00
Jakob Stoklund Olesen
f41b1697fe Add support for partial redefs to the fast register allocator. 
A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.

Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.

llvm-svn: 104167
 2010-05-19 21:36:05 +00:00
Devang Patel
d0b5830f72 There is no need to maintain InsnsBeginScopeSet separately. 
llvm-svn: 104165
 2010-05-19 21:26:53 +00:00
Eric Christopher
8c8d643a87 A more combo tls testcase. 
llvm-svn: 104163
 2010-05-19 21:19:42 +00:00
Jakob Stoklund Olesen
56998cc8aa Add MachineInstr::readsVirtualRegister() in preparation for proper handling of 
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

llvm-svn: 104149
 2010-05-19 20:36:22 +00:00
Eric Christopher
6b51010080 Few more simple tls testcases. 
llvm-svn: 104148
 2010-05-19 20:35:15 +00:00
Evan Cheng
46e08acfa5 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
llvm-svn: 104147
 2010-05-19 20:19:50 +00:00
Jakob Stoklund Olesen
6a2bfde3c8 TwoAddressInstructionPass doesn't really know how to merge live intervals when 
lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

llvm-svn: 104146
 2010-05-19 20:08:00 +00:00
Mikhail Glushenkov
e3e13b67e2 llvmc: report an error if a child process segfaults. 
llvm-svn: 104145
 2010-05-19 19:24:32 +00:00
Eric Christopher
fd72aa1040 Attempt to run this test on x86 only. 
llvm-svn: 104143
 2010-05-19 18:59:37 +00:00
Bob Wilson
e5f623ac22 Testcase to go with 104141. 
llvm-svn: 104142
 2010-05-19 18:58:37 +00:00
Bob Wilson
ae9655920b When expanding a vector_shuffle, the element type may not be legal and may 
need to be promoted.  The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion.  This fixes part of pr7167.

llvm-svn: 104141
 2010-05-19 18:48:32 +00:00
Daniel Dunbar
bfb199781d MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode(). 
llvm-svn: 104122
 2010-05-19 17:20:58 +00:00
Daniel Dunbar
9646c49298 MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same 
prefix byte problem as in r104062.
 - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.

llvm-svn: 104120
 2010-05-19 15:26:43 +00:00
Daniel Dunbar
12e2ce6164 MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and 
CALL64pcrel32, for the same reason.

llvm-svn: 104116
 2010-05-19 08:07:12 +00:00
Evan Cheng
6f52107b12 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. 
llvm-svn: 104115
 2010-05-19 07:28:01 +00:00
Evan Cheng
d4118b6c8d Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable. 
llvm-svn: 104114
 2010-05-19 07:26:50 +00:00
Tobias Grosser
52e991f3dd Update autoconf/automake versions in the documentation to match the versions used in Autogen.sh 
llvm-svn: 104113
 2010-05-19 07:00:17 +00:00
Daniel Dunbar
8d60e90859 MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate. 
llvm-svn: 104112
 2010-05-19 06:20:44 +00:00
Evan Cheng
0aa58d5b69 Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
llvm-svn: 104111
 2010-05-19 06:07:03 +00:00
Evan Cheng
b7657dfa38 Target instruction selection should copy memoperands. 
llvm-svn: 104110
 2010-05-19 06:06:09 +00:00
Daniel Dunbar
b5277e8ca0 MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to 
avoid same prefix byte problem as in r104062.

llvm-svn: 104108
 2010-05-19 04:31:36 +00:00
Evan Cheng
23fb523b44 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. 
llvm-svn: 104102
 2010-05-19 01:52:25 +00:00
Dan Gohman
434b54846d Add a comment explaining why this code uses Append mode. 
llvm-svn: 104095
 2010-05-19 01:21:34 +00:00
Evan Cheng
632cb17357 Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. 
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094
 2010-05-19 01:08:17 +00:00
Dan Gohman
f3685dcdc9 Factor out the code for picking integer arithmetic with immediate 
opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.

llvm-svn: 104091
 2010-05-19 00:53:19 +00:00
Eric Christopher
aec869777c Add a test to make sure that we're lowering the shift amount correctly. 
llvm-svn: 104090
 2010-05-19 00:22:04 +00:00
Dan Gohman
cdb7b1c110 Add a comment. 
llvm-svn: 104089
 2010-05-18 23:55:57 +00:00
Dan Gohman
d81303e044 Fix the predicate which checks for non-sensical formulae which have 
constants in registers which partially cancel out their immediate fields.

llvm-svn: 104088
 2010-05-18 23:48:08 +00:00
Dan Gohman
3a470a6b6c Factor out the code for recomputing an LSRUse's Regs set after some 
of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.

llvm-svn: 104087
 2010-05-18 23:42:37 +00:00
Bob Wilson
4872944eb3 Fix a crash when debugging the coalescer. DebugValue instructions are not 
in the coalescer's instruction map.

llvm-svn: 104086
 2010-05-18 23:19:42 +00:00
Dan Gohman
a58ace4036 Factor out code for estimating search space complexity into a helper 
function.

llvm-svn: 104082
 2010-05-18 22:51:59 +00:00
Dan Gohman
60d6263fde Add some more debug output. 
llvm-svn: 104080
 2010-05-18 22:41:32 +00:00
Dan Gohman
22ae418189 Factor out the code for deleting a formula from an LSRUse into 
a helper function.

llvm-svn: 104079
 2010-05-18 22:39:15 +00:00
Dan Gohman
9c986cbbe9 Make some debug output more informative. 
llvm-svn: 104078
 2010-05-18 22:37:37 +00:00
Dan Gohman
2a14bbdf13 Print an error message in Formula::print if the HasBaseReg flag 
is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.

llvm-svn: 104077
 2010-05-18 22:35:55 +00:00
Dan Gohman
649a99b8e8 Rename RegUseTracker's RegUses member to RegUsesMap to avoid 
confusion with LSRInstance's RegUses member.

llvm-svn: 104076
 2010-05-18 22:33:00 +00:00
Jakob Stoklund Olesen
f3114dbb3a Remember to update VirtRegLastUse when spilling without killing before a call. 
llvm-svn: 104074
 2010-05-18 22:20:09 +00:00
Dan Gohman
42a89be283 Teach mode load folding and unfolding code about CMP32ri8 and friends. 
llvm-svn: 104068
 2010-05-18 21:54:15 +00:00
Bill Wendling
5f00aa7459 Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is 
specified.

llvm-svn: 104066
 2010-05-18 21:47:08 +00:00
Dan Gohman
eaa3ee65bd When converting a test to a cmp to fold a load, use the cmp that has an 
8-bit immediate field rather than one with a wider immediate field.

llvm-svn: 104064
 2010-05-18 21:42:03 +00:00
Eric Christopher
79cbb29471 Quick test to make sure we're emitting the tbss section correctly. 
llvm-svn: 104063
 2010-05-18 21:40:20 +00:00
Chris Lattner
b1e6d120fc make mcinstlower remove all but the first operand to CALL64pcrel32. 
The register use operands (e.g. the first argument is passed in a 
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use.  This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.

This fixes rdar://7998435

llvm-svn: 104062
 2010-05-18 21:40:18 +00:00
Evan Cheng
e2980af336 Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
llvm-svn: 104060
 2010-05-18 21:31:17 +00:00
Eric Christopher
3f0aa8bf21 Implement EmitTBSSSymbol for MachOStreamer. 
Fixes build failure as well.

llvm-svn: 104059
 2010-05-18 21:26:41 +00:00
mike-m
f12653f97d Fix enum to address array bounds regression. 
llvm-svn: 104058
 2010-05-18 21:22:12 +00:00
Eric Christopher
4a9013f115 Make EmitTBSSSymbol take a section argument so that we can find it later. 
Fix up callers and users.

llvm-svn: 104057
 2010-05-18 21:16:04 +00:00
Jakob Stoklund Olesen
1d0a54cb9d Properly handle multiple definitions of a virtual register in the same 
instruction.

This can happen on ARM:

>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>

llvm-svn: 104056
 2010-05-18 21:10:50 +00:00