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200822 Commits

Author SHA1 Message Date
Amy Kwan
dedffec69e [PowerPC] Implement Truncate and Store VSX Vector Builtins
This patch implements the `vec_xst_trunc` function in altivec.h in  order to
utilize the Store VSX Vector Rightmost [byte | half | word | doubleword] Indexed
instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82467
2020-07-24 19:22:39 -05:00
Jessica Paquette
b6d2a38769 [AArch64][GlobalISel] Use wzr/xzr for 16 and 32 bit stores of zero
We weren't performing this optimization on 16 and 32 bit stores. SDAG happily
does this though.

e.g. https://godbolt.org/z/cWocKr

This saves about 0.2% in code size on CTMark at -O3.

Differential Revision: https://reviews.llvm.org/D84568
2020-07-24 17:15:20 -07:00
Rong Xu
27560ce987 [PGO][InstrProf] Do not promote count if the exit blocks contains ret instruction
Skip profile count promotion if any of the ExitBlocks contains a ret
instruction. This is to prevent dumping of incomplete profile -- if the
the loop is a long running loop and dump is called in the middle
of the loop, the result profile is incomplete.

ExitBlocks containing a ret instruction is an indication of a long running
loop -- early exit to error handling code.

Differential Revision: https://reviews.llvm.org/D84379
2020-07-24 17:13:58 -07:00
Matt Arsenault
16ca0e0369 GlobalISel: Define mulfix/divfix opcodes
The full expansion involves the funnel shifts, which depend on another
patch to expand those.
2020-07-24 20:02:20 -04:00
Amara Emerson
8f9bed84e6 [AArch64][GlobalISel] Promote G_UITOFP vector operands to same elt size as result.
Fixes legalization failures.
2020-07-24 17:00:50 -07:00
Alina Sbirlea
0651a23551 Reapply "[DomTree] Replace ChildrenGetter with GraphTraits over GraphDiff."
This is the part of the patch that's moving the Updates to a CFGDiff
object. Splitting off from the clean-up work merging the two branches when BUI is null.

Differential Revision: https://reviews.llvm.org/D77341
2020-07-24 14:10:50 -07:00
Matt Arsenault
26921b3bb5 AMDGPU: Skip other terminators before inserting s_cbranch_exec[n]z
PHIElimination/createPHISourceCopy inserts non-branch terminators
after the control flow pseudo if a successor phi reads a register
defined by the control flow pseudo. If this happens, we need to split
the expansion of the control flow pseudo to ensure all the branches
are after all of the other mask management instructions.

GlobalISel hit this in testscases that happened to be tail
duplicated. The original testcase still does not work, since the same
problem appears to be present in a later pass.
2020-07-24 16:51:59 -04:00
Eli Friedman
d2a7f965f0 [AArch64][SVE] Add "fast" fcmp operations.
dacf8d3 added support for most fcmp operations, but there are some extra
variations I hadn't considered: SelectionDAG supports float comparisons
that are neither ordered nor unordered. Add support for the missing
operations.

Differential Revision: https://reviews.llvm.org/D84460
2020-07-24 13:22:41 -07:00
Johannes Doerfert
b8680170b1 [SROA] Teach promote to register about droppable instructions
This is the second of two patches to address PR46753. We basically allow
SROA to promote allocas that are used in doppable instructions, for
now that means `llvm.assume`. The (transitive) uses are replaced by
`undef` in the droppable instructions.

See also D83976.

Reviewed By: Tyker

Differential Revision: https://reviews.llvm.org/D83978
2020-07-24 15:15:39 -05:00
Johannes Doerfert
ac3ceab3a2 [Mem2Reg] Teach promote to register about droppable instructions
This is the first of two patches to address PR46753. We basically allow
mem2reg to promote allocas that are used in doppable instructions, for
now that means `llvm.assume`. The uses of the alloca (or a bitcast or
zero offset GEP from there) are replaced by `undef` in the droppable
instructions.

Reviewed By: Tyker

Differential Revision: https://reviews.llvm.org/D83976
2020-07-24 15:15:38 -05:00
Johannes Doerfert
e393443e6f [SROA][Mem2Reg] Do not crash on alloca + addrspacecast
SROA knows that it can look through addrspacecast but
PromoteMemoryToRegister did not handle them. This caused an assertion
error for the test case, exposed while running
`Transforms/PhaseOrdering/inlining-alignment-assumptions.ll` with D83978
applied.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D84085
2020-07-24 15:15:38 -05:00
Gui Andrade
519182b1ba [MSAN] Allow inserting array checks
Flattens arrays by ORing together all their elements.

Differential Revision: https://reviews.llvm.org/D84446
2020-07-24 20:12:58 +00:00
Nemanja Ivanovic
fe8cc25a97 [PowerPC] Fix computation of offset for load-and-splat for permuted loads
Unfortunately this is another regression from my canonicalization patch
(1fed131660b2). The patch contained two implicit assumptions:
1. That we would have a permuted load only if we are loading a partial vector
2. That a partial vector load would necessarily be as wide as the splat

However, assumption 2 is not correct since it is possible to do a wider
load and only splat a half of it. This patch corrects this assumption by
simply checking if the load is permuted and adjusting the offset if it is.
2020-07-24 15:38:46 -04:00
Martin Storsjö
1d7926a981 [MC] [COFF] Make sure that weak external symbols are undefined symbols
For comdats (e.g. caused by -ffunction-sections), Section is already
set here; make sure it's null, for the weak external symbol to be undefined.

This fixes PR46779.

Differential Revision: https://reviews.llvm.org/D84507
2020-07-24 22:15:08 +03:00
Martin Storsjö
e8a94ed276 [llvm-lib] Support adding short import library objects with llvm-lib
This fixes PR 42837.

Differential Revision: https://reviews.llvm.org/D84465
2020-07-24 22:15:08 +03:00
Arthur Eubanks
b8cfb14c48 Rename scoped-noalias -> scoped-noalias-aa
Summary: To match NewPM name. Also the new name is clearer and more consistent.

Subscribers: jvesely, nhaehnle, hiraditya, asbirlea, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D84542
2020-07-24 12:14:27 -07:00
Valentin Clement
d92fc8cf98 [openmp] Clean up OMPKinds.def remove OMP_DIRECTIVE
This patch removes the OMP_DIRECTIVE definition from OMPKinds.def since they
are now defined in OMP.td and OMP_DIRECTIVE is not used anymore in the code.

Reviewed By: jdenny

Differential Revision: https://reviews.llvm.org/D84329
2020-07-24 15:06:54 -04:00
madhur13490
2e4d158121 [AMDGPU] Fix incorrect arch assert while setting up FlatScratchInit
Reviewers: arsenm, foad, rampitec, scott.linder

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D84391
2020-07-24 18:19:04 +00:00
Craig Topper
a1cd135fcb [X86] Move the implicit enabling of sse2 for 64-bit mode from X86Subtarget::initSubtargetFeatures to X86_MC::ParseX86Triple.
ParseX86Triple already checks for 64-bit mode and produces a
static string. We can just add +sse2 to the end of that static
string. This avoids a potential reallocation when appending it
to the std::string at runtime.

This is a slight change to the behavior of tools that only use
MC layer which weren't implicitly enabling sse2 before, but will
now. I don't think we check for sse2 explicitly in any MC layer
components so this shouldn't matter in practice. And if it did
matter the new behavior is more correct.
2020-07-24 11:14:20 -07:00
Francesco Petrogalli
5f0a55fcfc [llvm][sve] Reg + Imm addressing mode for ld1ro.
Reviewers: kmclaughlin, efriedma, sdesmalen

Subscribers: tschuett, hiraditya, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83357
2020-07-24 17:48:47 +00:00
Craig Topper
ab68f0ac7c [X86] Use X86_MC::ParseX86Triple to add mode features to feature string in X86Subtarget::initSubtargetFeatures.
Remove mode flags from constructor and remove calls to
ToggleFeature for the mode bits.

By adding them to the feature string we handle initializing the
mode member variables in X86Subtarget and the feature bits in
MCSubtargetInfo in one shot.
2020-07-24 10:48:22 -07:00
Meera Nakrani
079a983f02 [ARM] Added additional patterns to VABD instruction
Added extra patterns to VABD instruction so it is selected in place of VSUB and VABS. Added corresponding regression test too.

Differential Revision: https://reviews.llvm.org/D84500
2020-07-24 17:46:25 +00:00
Roman Lebedev
c94483e1b2 [NFC][GVN] Improve loadpre-missed-opportunity.ll test again thanks to @fhahn 2020-07-24 20:32:51 +03:00
Meera Nakrani
1e66b99fc0 Test Commit
Test commit - added whitespace in ARMInstrMVE.td
2020-07-24 17:22:56 +00:00
biplmish
5f31a23be8 [test commit] Add my name to the CREDITS.TXT
Add my name to the CREDITS.TXT

This is my test commit. (NFC)

Differential Revision: https://reviews.llvm.org/D84488
2020-07-24 12:05:53 -05:00
Florian Hahn
d2b6a61e8f [ValueTracking] Check for ConstantExpr before using recursive helpers.
Make sure we do not call
constainsConstantExpression/containsUndefElement on ConstantExpression,
which is not supported.

In particular, containsUndefElement/constainsConstantExpression are only
supported on constants which are supported by getAggregateElement.

Unfortunately there's no convenient way to check if a constant supports
getAggregateElement, so just check for non-constantexpressions with
vector type. Other users of those functions do so too.

Reviewers: spatel, nikic, craig.topper, lebedev.ri, jdoerfert, aqjune

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D84512
2020-07-24 17:37:09 +01:00
Nicolai Hähnle
005524128f MachineBasicBlock: add printName method
Common up some existing MBB name printing logic into a single place.
Note that basic block dumping now prints the same set of attributes as
the MIRPrinter.

Change-Id: I8f022bbd922e831bc96d63143d7472c03282530b

Differential Revision: https://reviews.llvm.org/D83253
2020-07-24 18:18:09 +02:00
David Truby
5f24d6d570 [flang] Run non-gtest unit tests with lit.
Summary:
As a corrollary, these tests are now run as part of the check-flang
target.

Reviewers: sscalpone

Subscribers: mgorny, delcypher, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83946
2020-07-24 14:49:39 +01:00
Dmitry Preobrazhensky
b97601342c [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
Currently supported LLVM MTBUF syntax is shown below. It is not compatible with SP3.

    op     dst, addr, rsrc, FORMAT, soffset

This change adds support for SP3 syntax:

    op     dst, addr, rsrc, soffset SP3FORMAT

In addition to being compatible with SP3, this syntax allows using symbolic names for data, numeric and unified formats. Below is a list of added syntax variants.

format:<expression>
format:[<numeric-format-name>,<data-format-name>]
format:[<data-format-name>,<numeric-format-name>]
format:[<data-format-name>]
format:[<numeric-format-name>]
format:[<unified-format-name>]

The last syntax variant is supported for GFX10 only.

See llvm bug 37738

Reviewers: arsenm, rampitec, vpykhtin

Differential Revision: https://reviews.llvm.org/D84026
2020-07-24 16:41:03 +03:00
Nico Weber
fc0b2943f1 [gn build] (manually) port 10b1b4a23 more 2020-07-24 08:48:14 -04:00
Nico Weber
54f4b4b6c4 [gn build] (manually) port 10b1b4a23 2020-07-24 08:37:57 -04:00
Djordje Todorovic
a300c4e233 [DWARF][EntryValues] Emit GNU extensions in the case of DWARF 4 + SCE
Emit DWARF 5 call-site symbols even though DWARF 4 is set,
only in the case of LLDB tuning.

This patch addresses PR46643.

Differential Revision: https://reviews.llvm.org/D83463
2020-07-24 14:33:57 +02:00
Nico Weber
5622d0e657 [gn build] (manually) port 228f8d89 2020-07-24 08:29:36 -04:00
Simon Pilgrim
a4fb77451c Revert rG5dd566b7c7b78bd- "PassManager.h - remove unnecessary Function.h/Module.h includes. NFCI."
This reverts commit 5dd566b7c7b78bd385418c72d63c79895be9ae97.

Causing some buildbot failures that I'm not seeing on MSVC builds.
2020-07-24 13:02:33 +01:00
Simon Pilgrim
32d0701fa1 PassManager.h - remove unnecessary Function.h/Module.h includes. NFCI.
PassManager.h is one of the top headers in the ClangBuildAnalyzer frontend worst offenders list.

This exposes a large number of implicit dependencies on various forward declarations/includes in other headers that need addressing.
2020-07-24 12:40:50 +01:00
Djordje Todorovic
d652c017f2 [DWARF] Avoid entry_values production for SCE
SONY debugger does not prefer debug entry values feature, so
the plan is to avoid production of the entry values
by default when the tuning is SCE debugger.

The feature still can be enabled with the -debug-entry-values
option for the testing/development purposes.

This patch addresses PR46643.

Differential Revision: https://reviews.llvm.org/D83462
2020-07-24 13:34:05 +02:00
Georgii Rymar
0d030a773a [obj2yaml][yaml2obj] - Add note-section.yaml tests.
They were a part of D68983, but were lost in the last
diff and were not committed for unknown reason.

I've renamed (from elf-sht-note.yaml) them and fixed
broken formating a few places. Everything else remained
untouched.
2020-07-24 14:27:54 +03:00
Roman Lebedev
8acafe5379 [NFC][GVN] Clean loadpre-missed-opportunity.ll test some more 2020-07-24 12:44:22 +03:00
Florian Hahn
55c3c49e06 [IPSCCP] Add another test case with argmemonly callsite attributes. 2020-07-24 10:13:51 +01:00
Xing GUO
9f9286af5c [DWARFYAML] Replace 'Format', 'Version', etc with 'FormParams'. NFC.
This patch replaces 'Format', 'Version' fields, etc with 'FormParams' to
simplify codes.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D84496
2020-07-24 16:54:51 +08:00
Petar Avramovic
8a0a38f0c4 AMDGPU/GlobalISel: Select set.inactive intrinsic
Differential Revision: https://reviews.llvm.org/D84407
2020-07-24 10:14:14 +02:00
Craig Topper
c93c5e72a0 [X86] Make the X86ProcFamilyEnum private to X86Subtarget. Removed unneeded 'protected' from X86Subtarget. NFC 2020-07-23 23:42:11 -07:00
Petr Hosek
300de51f92 [CMake] Simplify CMake handling for zlib
Rather than handling zlib handling manually, use find_package from CMake
to find zlib properly. Use this to normalize the LLVM_ENABLE_ZLIB,
HAVE_ZLIB, HAVE_ZLIB_H. Furthermore, require zlib if LLVM_ENABLE_ZLIB is
set to YES, which requires the distributor to explicitly select whether
zlib is enabled or not. This simplifies the CMake handling and usage in
the rest of the tooling.

This is a reland of abb0075 with all followup changes and fixes that
should address issues that were reported in PR44780.

Differential Revision: https://reviews.llvm.org/D79219
2020-07-23 23:05:36 -07:00
Mircea Trofin
c07fcb7a55 [llvm][NFC] Don't use llvm/Config/config.h in .h files
config.h is excluded from installs, llvm-config.h isn't

Differential Revision: https://reviews.llvm.org/D84459
2020-07-23 22:27:38 -07:00
Xing GUO
8195cce4cd [DWARFYAML] Use writeDWARFOffset() to simplify emitting offsets. NFC.
This patch uses writeDWARFOffset() to simplify some codes. NFC.
2020-07-24 12:15:18 +08:00
Nico Weber
2add9f8975 [gn build] (manually) merge d054c7ee2e9 2020-07-23 22:28:23 -04:00
Fangrui Song
4f0382f382 Add test utility 'extract'
See https://lists.llvm.org/pipermail/llvm-dev/2020-July/143373.html
"[llvm-dev] Multiple documents in one test file" for some discussions.

`extract part filename` splits the input file into multiple parts separated by
regex `^(.|//)--- ` and extract the specified part to stdout or the
output file (if specified).

Use case A (organizing input of different formats (e.g. linker
script+assembly) in one file).

```
// RUN: extract lds %s -o %t.lds
// RUN: extract asm %s -o %t.s
// RUN: llvm-mc %t.s -o %t.o
// RUN: ld.lld -T %t.lds %t.o -o %t
This is sometimes better than the %S/Inputs/ approach because the user
can see the auxiliary files immediately and don't have to open another file.
```

Use case B (for utilities which don't have built-in input splitting
feature):

```
// RUN: extract case1 %s | llc | FileCheck %s --check-prefix=CASE1
// RUN: extract case2 %s | llc | FileCheck %s --check-prefix=CASE2
Combing tests prudently can improve readability.
This is sometimes better than having multiple test files.
```

Since this is a new utility, there is no git history concerns for
UpperCase variable names. I use lowerCase variable names like mlir/lld.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D83834
2020-07-23 19:15:35 -07:00
Craig Topper
a70e8e80f8 [LegalizeTypes] Teach DAGTypeLegalizer::GenWidenVectorLoads to pad with undef if needed when concatenating small or loads to match a larger load
In the included test case the align 16 allowed the v23f32 load to handled as load v16f32, load v4f32, and load v4f32(one element not used). These loads all need to be concatenated together into a final vector. In this case we tried to concatenate the two v4f32 loads to match the type of the v16f32 load so we could do a second concat_vectors, but those loads alone only add up to v8f32. So we need to two v4f32 undefs to pad it.

It appears we've tried to hack around a similar issue in this code before by adding undef padding to loads in one of the earlier loops in this function. Originally in r147964 by padding all loads narrower than previous loads to the same size. Later modifed to only the last load in r293088. This patch removes that earlier code and just handles it on demand where we know we need it.

Fixes PR46820

Differential Revision: https://reviews.llvm.org/D84463
2020-07-23 19:02:03 -07:00
Matt Arsenault
929709ee06 GlobalISel: Add scalarSameSizeAs LegalizeRule
Widen or narrow a type to a type with the same scalar size as
another. This can be used to force G_PTR_ADD/G_PTRMASK's scalar
operand to match the bitwidth of the pointer type. Use this to
disallow narrower types for G_PTRMASK.
2020-07-23 21:17:31 -04:00
Matt Arsenault
4fa5e95608 GlobalISel: Drop original type pointeriness in minScalarSameAs
It is not useful to report WidenScalar for a pointer value, so always
report a scalar value with the target size. This allows using this to
clamp the scalar operand to the pointer size in operations like
G_PTR_ADD or G_PTRMASK.
2020-07-23 21:17:18 -04:00