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6195ace4c0
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2043 Commits

Author SHA1 Message Date
Dale Johannesen
6195ace4c0 Implement the real calling convention for ppc32 Altivec: 
vectors go at the end of the memory area, after all
non-vector parameters.

llvm-svn: 48364
 2008-03-14 17:41:26 +00:00
Dale Johannesen
1e54f7c2b6 Do not promote float params to double in varargs 
calls here.  This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.

llvm-svn: 48310
 2008-03-12 23:40:01 +00:00
Dale Johannesen
19b4c2dfaf One more bit of Altivec parameter passing. 
llvm-svn: 48269
 2008-03-12 00:49:20 +00:00
Dale Johannesen
460dc31418 Implement Altivec passing to varargs functions on ppc. 
llvm-svn: 48264
 2008-03-12 00:22:17 +00:00
Dan Gohman
8e3c88c4e9 Use PassManagerBase instead of FunctionPassManager for functions 
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256
 2008-03-11 22:29:46 +00:00
Dan Gohman
85bfbe2293 Generalize ExpandIntToFP to handle the case where the operand is legal 
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 

llvm-svn: 48206
 2008-03-11 01:59:03 +00:00
Dale Johannesen
3278acdaaa Disable prolog code that aligns the stack when a 
local object of >16 byte alignment exists.  It does not
work and getting it to work is not trivial, as explained
in the comment.  This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.

(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec.  So I think disabling it is OK.)

llvm-svn: 48188
 2008-03-10 22:59:46 +00:00
Bill Wendling
80bc045af5 Change the "enable/disable" mechanism so that we can enable PPC register 
scavenging for 32-bit and 64-bit separately.

llvm-svn: 48186
 2008-03-10 22:49:16 +00:00
Evan Cheng
7d9e5a7680 Default ISD::PREFETCH to expand. 
llvm-svn: 48169
 2008-03-10 19:38:10 +00:00
Chris Lattner
52be2c645e fix 80 col violations. 
llvm-svn: 48166
 2008-03-10 18:55:53 +00:00
Nicolas Geoffray
a904844534 Stylistic modifications. No functionality changes. 
llvm-svn: 48158
 2008-03-10 17:46:45 +00:00
Scott Michel
bb8e8fca47 Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's 
return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.

llvm-svn: 48145
 2008-03-10 15:42:14 +00:00
Nicolas Geoffray
e3381f0f1f Add description of individual bits in CR. This fix PR1765. 
llvm-svn: 48143
 2008-03-10 14:12:10 +00:00
Dale Johannesen
e6b0009792 Increase ISD::ParamFlags to 64 bits. Increase the ByValSize 
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff.  Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and 
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)

llvm-svn: 48122
 2008-03-10 02:17:22 +00:00
Chris Lattner
4a5abdbe3f Darwin PPC64 indirect call target goes in X12, not R12. This fixes these 
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll

llvm-svn: 48120
 2008-03-09 20:49:33 +00:00
Dale Johannesen
55d6e1a5aa More ppc32 byval handling (bug fixes). Things 
are looking pretty good now.

llvm-svn: 48043
 2008-03-08 01:41:42 +00:00
Evan Cheng
dba1dfe962 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. 
llvm-svn: 48042
 2008-03-08 00:58:38 +00:00
Dan Gohman
afeac8050d Add support for calls with i128 return values on ppc64. 
llvm-svn: 48041
 2008-03-08 00:19:12 +00:00
Bill Wendling
948c50e2be PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this 
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.

llvm-svn: 48030
 2008-03-07 20:49:02 +00:00
Dan Gohman
5bf464e1e6 Add support for lowering 128-bit shifts on ppc64. 
llvm-svn: 48029
 2008-03-07 20:36:53 +00:00
Dale Johannesen
3e6bacf7be Next bits of PPC byval handling. Basically functional 
but there are bugs.

llvm-svn: 48028
 2008-03-07 20:27:40 +00:00
Chris Lattner
08ec4919ea Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl). 
llvm-svn: 48027
 2008-03-07 20:18:24 +00:00
Chris Lattner
2f13ccc181 Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work 
with 32 or 64-bit operands/results.

llvm-svn: 48026
 2008-03-07 20:13:51 +00:00
Dale Johannesen
6bcc9808db Next bit of PPC ByVal handling; call-site code seems 
correct now.

llvm-svn: 47978
 2008-03-05 23:31:27 +00:00
Bill Wendling
37f5b4586a Removed spurious EnablePPCRS check. 
llvm-svn: 47918
 2008-03-04 23:27:33 +00:00
Dale Johannesen
86867d323e Move PPC lowering functions into PPCTargetLowering 
class (cosmetic).  First piece of byval implementation;
this doesn't work yet.  No functional change.

llvm-svn: 47917
 2008-03-04 23:17:14 +00:00
Bill Wendling
dc9de245cb Use a command-line option to turn register scavenging on/off for PPC. 
llvm-svn: 47915
 2008-03-04 23:13:51 +00:00
Bill Wendling
8d64999daf This is the initial check-in for adding register scavenging to PPC. (Currently, 
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.

llvm-svn: 47863
 2008-03-03 22:19:16 +00:00
Chris Lattner
f2a9b32eec add a note 
llvm-svn: 47830
 2008-03-02 19:27:34 +00:00
Chris Lattner
4c67781884 Evan implemented this. 
llvm-svn: 47827
 2008-03-02 17:56:29 +00:00
Anton Korobeynikov
875da2420a Use enumeration for preffered EH dwarf encoding reason 
llvm-svn: 47770
 2008-02-29 22:09:08 +00:00
Dale Johannesen
310201ba32 Interface of getByValTypeAlignment differed between 
generic & x86 versions; change generic to follow x86
and improve comments.  Add PPC version (not right
for non-Darwin.)

llvm-svn: 47734
 2008-02-28 22:31:51 +00:00
Evan Cheng
f8b1257d2e Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. 
llvm-svn: 47703
 2008-02-28 00:43:03 +00:00
Anton Korobeynikov
f8d5799001 EHPreferredDataFormat hook for PPC targets. Looks like Darwin 
uses the same encoding everywhere. Linux FIXME'ed.

llvm-svn: 47701
 2008-02-27 23:49:15 +00:00
Dan Gohman
5d96a06b0b Don't hard-code the mask size to be 32, which is incorrect on ppc64 
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.

llvm-svn: 47692
 2008-02-27 21:12:32 +00:00
Bill Wendling
2cae66e28b Final de-tabification. 
llvm-svn: 47663
 2008-02-27 06:33:05 +00:00
Dan Gohman
938e74654b Convert the last remaining users of the non-APInt form of 
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.

llvm-svn: 47654
 2008-02-27 01:23:58 +00:00
Bill Wendling
8fb166bf6c Rename PrintableName to Name. 
llvm-svn: 47629
 2008-02-26 21:47:57 +00:00
Bill Wendling
50f5c4be14 Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool 
would have been a Godsend here!

llvm-svn: 47625
 2008-02-26 21:11:01 +00:00
Bill Wendling
a369a6add8 Some platforms use the same name for 32-bit and 64-bit registers (like 
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.

llvm-svn: 47534
 2008-02-24 00:56:13 +00:00
Anton Korobeynikov
4f6e612973 Remove bunch of gcc 4.3-related warnings from Target 
llvm-svn: 47369
 2008-02-20 11:22:39 +00:00
Andrew Lenharth
da54523742 I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. 
llvm-svn: 47213
 2008-02-16 14:46:26 +00:00
Chris Lattner
d55c26a77d Handle \n's in value names for more targets. The asm printers 
really really really need refactoring :(

llvm-svn: 47171
 2008-02-15 19:04:54 +00:00
Dale Johannesen
b9e1a37497 Cosmetics. 
llvm-svn: 47168
 2008-02-15 18:40:53 +00:00
Dale Johannesen
de53aaec39 Remove warning about 64-bit code on processor 
that doesn't support it.  Per Chris.

llvm-svn: 47162
 2008-02-15 18:09:51 +00:00
Dale Johannesen
6cb8a628a2 Rewrite tblgen handling of subtarget features so 
it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to.  Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.

llvm-svn: 47143
 2008-02-14 23:35:16 +00:00
Nate Begeman
1ef1013b6c Change how FP immediates are handled. 
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
   if it is legal.

This allows ConstantFP to be handled like Constant, allowing for 
targets that can encode FP immediates as MachineOperands.

As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants!  Hooray.

llvm-svn: 47121
 2008-02-14 08:57:00 +00:00
Dan Gohman
99b38405e3 Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits 
to pass the mask APInt by value, not by reference. 

llvm-svn: 47096
 2008-02-13 22:28:48 +00:00
Nicolas Geoffray
72fa78e195 Enable exception handling int JIT 
llvm-svn: 47079
 2008-02-13 18:39:37 +00:00
Chris Lattner
80b3a56774 Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR. 
llvm-svn: 47067
 2008-02-13 17:24:14 +00:00