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Commit Graph

185220 Commits

Author SHA1 Message Date
DeForest Richards
636d7ad372 [Docs] Adds new page for Getting Involved articles
Adds a new page for existing Getting Involved, Development Process, and Community Proposals articles. Also moves Mailing Lists, Meetups and social events, and IRC sections.

llvm-svn: 372487
2019-09-21 20:56:40 +00:00
Martin Storsjo
f445330df3 [CodeView] Add pragma push/pop_macro for ARM64_FPSR to enum header
This fixes (one aspect of) compilation of LLDB with MSVC for ARM64.

LLDB source files include intrin.h, and the MSVC intrin.h transitively
includes arm64intr.h, which has an ARM64_FPSR define, which clashes
with the enum declaration.

Differential Revision: https://reviews.llvm.org/D67864

llvm-svn: 372481
2019-09-21 19:09:24 +00:00
Suyog Sarda
af782eed2a SROA: Check Total Bits of vector type
While Promoting alloca instruction of Vector Type, 
Check total size in bits of its slices too.
If they don't match, don't promote the alloca instruction.

Bug : https://bugs.llvm.org/show_bug.cgi?id=42585

llvm-svn: 372480
2019-09-21 18:16:37 +00:00
Suyog Sarda
cb411decd8 Test mail. NFC.
Testing commit acces. NFC.

llvm-svn: 372479
2019-09-21 18:03:30 +00:00
Wei Mi
b265118981 Recommit [SampleFDO] Expose an interface to return the size of a section
or the size of the profile for profile in ExtBinary format.

Fix a test failure on Mac.

[SampleFDO] Expose an interface to return the size of a section or the
size of the profile for profile in ExtBinary format.

Sometimes we want to limit the size of the profile by stripping some functions
with low sample count or by stripping some function names with small text size
from profile symbol list. That requires the profile reader to have the
interfaces returning the size of a section or the size of total profile. The
patch add those interfaces.

At the same time, add some dump facility to show the size of each section.

Differential revision: https://reviews.llvm.org/D67726

llvm-svn: 372478
2019-09-21 17:23:55 +00:00
Hideto Ueno
567fce3ca2 [Attributor] Implement "norecurse" function attribute deduction
Summary:
This patch introduces `norecurse` function attribute deduction.

`norecurse` will be deduced if the following conditions hold:
* The size of SCC in which the function belongs equals to 1.
* The function doesn't have self-recursion.
* We have `norecurse` for all call site.

To avoid a large change, SCC is calculated using scc_iterator in InfoCache initialization for now.

Reviewers: jdoerfert, sstefan1

Reviewed By: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67751

llvm-svn: 372475
2019-09-21 15:13:19 +00:00
Fangrui Song
9ccaf1473c [Support] Add a DataExtractor constructor that takes ArrayRef<uint8_t>
The new constructor can simplify some llvm-readobj call sites.

Reviewed By: grimar, dblaikie

Differential Revision: https://reviews.llvm.org/D67797

llvm-svn: 372473
2019-09-21 15:05:03 +00:00
DeForest Richards
407a0cb703 [Docs] Bug fix for document not included in toctree
Fixes 'document not included in toctree' bug for FAQ and Lexicon topics.

llvm-svn: 372470
2019-09-21 14:29:19 +00:00
DeForest Richards
9d5f019089 [Docs] Updates sidebar links
Adds additional links to sidebar. Also removes Glossary and FAQ from LLVM Design & Overview section. (These links now reside on the sidebar.)

llvm-svn: 372469
2019-09-21 14:17:09 +00:00
Roman Lebedev
c1a31b1e8e [NFC][X86] Adjust check prefixes in bmi.ll (PR43381)
llvm-svn: 372468
2019-09-21 11:12:55 +00:00
Amara Emerson
32510b606a [AArch64][GlobalISel] Implement selection for G_SHL of <2 x i64>
Simple continuation of existing selection support.

llvm-svn: 372467
2019-09-21 09:21:16 +00:00
Amara Emerson
5f6b7279f3 [AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>
Just add an extra case to the existing selection logic.

llvm-svn: 372466
2019-09-21 09:21:13 +00:00
Amara Emerson
a9369d64ec [AArch64][GlobalISel] Make <4 x s32> G_ASHR and G_LSHR legal.
llvm-svn: 372465
2019-09-21 09:21:10 +00:00
Amara Emerson
ac22fb5afc Revert "[SampleFDO] Expose an interface to return the size of a section or the size"
This reverts commit f118852046a1d255ed8c65c6b5db320e8cea53a0.

Broke the macOS build/greendragon bots.

llvm-svn: 372464
2019-09-21 09:11:51 +00:00
James Molloy
a040a966a9 [MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCount
Recommit: fix asan errors.

The way MachinePipeliner uses these target hooks is stateful - we reduce trip
count by one per call to reduceLoopCount. It's a little overfit for hardware
loops, where we don't have to worry about stitching a loop induction variable
across prologs and epilogs (the induction variable is implicit).

This patch introduces a new API:

  /// Analyze loop L, which must be a single-basic-block loop, and if the
  /// conditions can be understood enough produce a PipelinerLoopInfo object.
  virtual std::unique_ptr<PipelinerLoopInfo>
  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const;

The return value is expected to be an implementation of the abstract class:

  /// Object returned by analyzeLoopForPipelining. Allows software pipelining
  /// implementations to query attributes of the loop being pipelined.
  class PipelinerLoopInfo {
  public:
    virtual ~PipelinerLoopInfo();
    /// Return true if the given instruction should not be pipelined and should
    /// be ignored. An example could be a loop comparison, or induction variable
    /// update with no users being pipelined.
    virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;

    /// Create a condition to determine if the trip count of the loop is greater
    /// than TC.
    ///
    /// If the trip count is statically known to be greater than TC, return
    /// true. If the trip count is statically known to be not greater than TC,
    /// return false. Otherwise return nullopt and fill out Cond with the test
    /// condition.
    virtual Optional<bool>
    createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
                                 SmallVectorImpl<MachineOperand> &Cond) = 0;

    /// Modify the loop such that the trip count is
    /// OriginalTC + TripCountAdjust.
    virtual void adjustTripCount(int TripCountAdjust) = 0;

    /// Called when the loop's preheader has been modified to NewPreheader.
    virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;

    /// Called when the loop is being removed.
    virtual void disposed() = 0;
  };

The Pipeliner (ModuloSchedule.cpp) can use this object to modify the loop while
allowing the target to hold its own state across all calls. This API, in
particular the disjunction of creating a trip count check condition and
adjusting the loop, improves the code quality in ModuloSchedule.cpp.

llvm-svn: 372463
2019-09-21 08:19:41 +00:00
Craig Topper
ef72bd9cc3 [X86] Use sse_load_f32/f64 and timm in patterns for memory form of vgetmantss/sd.
Previously we only matched scalar_to_vector and scalar load, but
we should be able to narrow a vector load or match vzload.

Also need to match TargetConstant instead of Constant. The register
patterns were previously updated, but not the memory patterns.

llvm-svn: 372458
2019-09-21 06:44:29 +00:00
Craig Topper
717f1d9695 [X86] Add test case to show failure to fold load with getmantss due to isel pattern looking for Constant instead of TargetConstant
The intrinsic has an immarg so its gets created with a TargetConstant
instead of a Constant after r372338. The isel pattern was only
updated for the register form, but not the memory form.

llvm-svn: 372457
2019-09-21 06:44:24 +00:00
Nico Weber
97767c6eb1 avr targetinfo: remove unneeded dep on MC
llvm-svn: 372451
2019-09-21 02:43:32 +00:00
Matt Arsenault
c078733972 AMDGPU/GlobalISel: Allow selection of scalar min/max
I believe all of the uniform/divergent pattern predicates are
redundant and can be removed. The uniformity bit already influences
the register class, and nothhing has broken when I've removed this and
others.

llvm-svn: 372450
2019-09-21 02:37:33 +00:00
Matt Arsenault
ae65fbf0a9 LiveIntervals: Add missing operator!= for segments
llvm-svn: 372449
2019-09-21 02:37:28 +00:00
Artur Pilipenko
5cc8a158ad Support for 64-bit PC-relative relocations for X86_64
ELF files generated for X86_64 targets may contain 64-bit PC-relative 
relocations. For instance, an exception handler table entry contains the start 
of exception-throwing frame relative to the start of exception handler. As these 
two labels belong to different sections, their difference and so the relocation 
is 64-bit.

An attempt to parse such file, i.e. in DWARFContext::create, results in "failed 
to compute relocation" error.

This fix adds support for such relocations to RelocationResolver.cpp.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D67779

Patch by Oleg Pliss (Oleg.Pliss@azul.com)

llvm-svn: 372447
2019-09-21 01:37:14 +00:00
GN Sync Bot
40ff3514b8 gn build: Merge r372445
llvm-svn: 372446
2019-09-21 01:27:09 +00:00
Amara Emerson
860145b41c [GlobalISel] Defer setting HasCalls on MachineFrameInfo to selection time.
We currently always set the HasCalls on MFI during translation and legalization if
we're handling a call or legalizing to a libcall. However, if that call is later
optimized to a tail call then we don't need the flag. The flag being set to true
causes frame lowering to always save and restore FP/LR, which adds unnecessary code.

This change does the same thing as SelectionDAG and ports over some code that scans
instructions after selection, using TargetInstrInfo to determine if target opcodes
are known calls.

Code size geomean improvements on CTMark:
 -O0 : 0.1%
 -Os : 0.3%

Differential Revision: https://reviews.llvm.org/D67868

llvm-svn: 372443
2019-09-20 23:52:07 +00:00
Teresa Johnson
104cb4adfc [Inliner] Remove incorrect early exit during switch cost computation
Summary:
The CallAnalyzer::visitSwitchInst has an early exit when the estimated
lower bound of the switch cost will put the overall cost of the inline
above the threshold. However, this code is not correctly estimating the
lower bound for switches that can be transformed into bit tests, leading
to unnecessary lost inlines, and also differing behavior with
optimization remarks enabled.

First, the early exit is controlled by whether ComputeFullInlineCost is
enabled or not, and that in turn is disabled by default but enabled when
enabling -pass-remarks=missed. This by itself wouldn't lead to a
problem, except that as described below, the lower bound can be above
the real lower bound, so we can sometimes get different inline decisions
with inline remarks enabled, which is problematic.

The early exit was added in along with a new switch cost model in D31085.
The reason why this early exit was added is due to a concern one reviewer
raised about compile time for large switches:
https://reviews.llvm.org/D31085?id=94559#inline-276200

However, the code just below there calls
getEstimatedNumberOfCaseClusters, which in turn immediately calls
BasicTTIImpl getEstimatedNumberOfCaseClusters, which in the worst case
does a linear scan of the cases to get the high and low values. The
bit test handling in particular is guarded by whether the number of
cases fits into the max bit width. There is no suggestion that anyone
measured a compile time issue, it appears to be theoretical.

The problem is that the reviewer's comment about the lower bound
calculation is incorrect, specifically in the case of a switch that can
be lowered to a bit test. This isn't followed up on the comment
thread, but the author does add a FIXME to that effect above the early
exit added when they subsequently revised the patch.

As a result, we were incorrectly early exiting and not inlining
functions with switch statements that would be lowered to bit tests in
cases where we were nearing the threshold. Combined with the fact that
this early exit was skipped with opt remarks enabled, this caused
different inlining decisions to be made when -pass-remarks=missed is
enabled to debug the missing inline.

Remove the early exit for the above reasons.

I also copied over an existing AArch64 inlining test to X86, and
adjusted the threshold so that the bit test inline only occurs with the
fix in this patch.

Reviewers: davidxl

Subscribers: eraman, kristof.beyls, haicheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67716

llvm-svn: 372440
2019-09-20 23:29:17 +00:00
Wei Mi
63f3fac875 [SampleFDO] Expose an interface to return the size of a section or the size
of the profile for profile in ExtBinary format.

Sometimes we want to limit the size of the profile by stripping some functions
with low sample count or by stripping some function names with small text size
from profile symbol list. That requires the profile reader to have the
interfaces returning the size of a section or the size of total profile. The
patch add those interfaces.

At the same time, add some dump facility to show the size of each section.

llvm-svn: 372439
2019-09-20 23:24:50 +00:00
Ulrich Weigand
8f9591eb21 [SystemZ] Support z15 processor name
The recently announced IBM z15 processor implements the architecture
already supported as "arch13" in LLVM.  This patch adds support for
"z15" as an alternate architecture name for arch13.

The patch also uses z15 in a number of places where we used arch13
as long as the official name was not yet announced.

llvm-svn: 372435
2019-09-20 23:04:45 +00:00
Sterling Augustine
fd7a9c638e Fix missed case of switching getConstant to getTargetConstant. Try 2.
Summary: This fixes a crasher introduced by r372338.

Reviewers: echristo, arsenm

Subscribers: wdng, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67850

llvm-svn: 372434
2019-09-20 22:26:55 +00:00
DeForest Richards
1f41a90eb5 [Docs] Add a custom sidebar to doc pages
Adds a custom sidebar to LLVM docs. Sidebar includes links to How to submit a bug and FAQ topics, as well as a Show Source link and search box.

llvm-svn: 372432
2019-09-20 22:16:39 +00:00
Simon Pilgrim
6fc569cfd8 [PPC] PPCLoopPreIncPrep - silence static analyzer null dereference warning.
llvm-svn: 372430
2019-09-20 21:27:49 +00:00
Simon Pilgrim
55ebed885d [AddressSanitizer] Don't dereference dyn_cast<ConstantInt> results. NFCI.
The static analyzer is warning about potential null dereference, but we can use cast<ConstantInt> directly and if not assert will fire for us.

llvm-svn: 372429
2019-09-20 20:52:21 +00:00
DeForest Richards
4d6ef7156b [Docs] Move topics to new categories
This commit moves several topics to new categories. 

llvm-svn: 372428
2019-09-20 20:51:33 +00:00
Jinsong Ji
b2118cf9ea [NFC][PowerPC] Consolidate testing of common linkage symbols
Add a new file to test the code gen for common linkage symbol.
Remove common linkage in some other testcases to avoid distraction.

llvm-svn: 372426
2019-09-20 20:31:37 +00:00
Mitch Phillips
1a7a7c7655 Revert "[MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCount"
This commit broke the ASan buildbot. See comments in rL372376 for more
information.

This reverts commit 15e27b0b6d9d51362fad85dbe95ac5b3fadf0a06.

llvm-svn: 372425
2019-09-20 20:25:16 +00:00
Matt Morehouse
e4d9769ce4 [docs] Update structure-aware-fuzzing link.
The document has been moved to the google/fuzzing GitHub repo.

llvm-svn: 372423
2019-09-20 19:39:50 +00:00
Michael Trent
3be1da20f7 Can't pass .dSYM directory to llvm-objdump -dsym= (and error message is wrong)
Summary:
Allow users to pass the path to a .dSYM directory to llvm-objdump's -dsym
flag rather than requiring users to find the DWARF DSYM Mach-O within the
bundle structure by hand.

rdar://46873333

Reviewers: pete, lhames, friss, aprantl

Reviewed By: pete, aprantl

Subscribers: MaskRay, aprantl, rupprecht, seiya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67780

llvm-svn: 372421
2019-09-20 19:13:24 +00:00
Craig Topper
d1d516ac0b [Mips] Remove immarg test for intrinsics that no longer have an immarg after r372409.
llvm-svn: 372420
2019-09-20 18:52:49 +00:00
Simon Pilgrim
cc17c8b584 Fix -Wdocumentation warning. NFCI.
llvm-svn: 372418
2019-09-20 18:21:31 +00:00
Jinsong Ji
cdca265e5e [NFC][PowerPC] Refactor classifyGlobalReference
We always(and only) check the NLP flag after calling
classifyGlobalReference to see whether it is accessed
indirectly.

Refactor to code to use isGVIndirectSym instead.

llvm-svn: 372417
2019-09-20 18:21:07 +00:00
Simon Pilgrim
01e34ad2fb Fix MSVC "not all control paths return a value" warning. NFCI.
llvm-svn: 372416
2019-09-20 18:10:17 +00:00
Roman Lebedev
f120f5204a [NFC][InstCombine] Fixup newly-added tests
llvm-svn: 372413
2019-09-20 17:43:46 +00:00
Evgeniy Stepanov
00275eb9d2 [MTE] Handle MTE instructions in AArch64LoadStoreOptimizer.
Summary: Generate pre- and post-indexed forms of ST*G and STGP when possible.

Reviewers: ostannard, vitalybuka

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67741

llvm-svn: 372412
2019-09-20 17:36:27 +00:00
Craig Topper
3369238fc2 [SelectionDAG][Mips][Sparc] Don't allow SimplifyDemandedBits to constant fold TargetConstant nodes to a Constant.
Summary:
After the switch in SimplifyDemandedBits, it tries to create a
constant when possible. If the original node is a TargetConstant
the default in the switch will call computeKnownBits on the
TargetConstant which will succeed. This results in the
TargetConstant becoming a Constant. But TargetConstant exists to
avoid being changed.

I've fixed the two cases that relied on this in tree by explicitly
making the nodes constant instead of target constant. The Sparc
case is an old bug. The Mips case was recently introduced now that
ImmArg on intrinsics gets turned into a TargetConstant when the
SelectionDAG is created. I've removed the ImmArg since it lowers
to generic code.

Reviewers: arsenm, RKSimon, spatel

Subscribers: jyknight, sdardis, wdng, arichardson, hiraditya, fedor.sergeev, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67802

llvm-svn: 372409
2019-09-20 16:49:51 +00:00
Sebastian Pop
4c4c86df5d [aarch64] add def-pats for dot product
This patch adds the patterns to select the dot product instructions.
Tested on aarch64-linux with make check-all.

Differential Revision: https://reviews.llvm.org/D67645

llvm-svn: 372408
2019-09-20 16:33:33 +00:00
Stanislav Mekhanoshin
8776a8f98e Remove assert from MachineLoop::getLoopPredecessor()
According to the documentation method returns predecessor
if the given loop's header has exactly one unique predecessor
outside the loop. Otherwise return null.

In reality it asserts if there is no predecessor outside of
the loop.

The testcase has the loop where predecessors outside of the
loop were not identified as analyzeBranch() was unable to
process the mask branch and returned true. That is also not
correct to assert for the truly dead loops.

Differential Revision: https://reviews.llvm.org/D67634

llvm-svn: 372405
2019-09-20 15:26:10 +00:00
Krzysztof Parzyszek
cfc0a1e836 [MVT] Add v256i1 to MachineValueType
This type can show up when lowering some HVX vector code on Hexagon.

llvm-svn: 372403
2019-09-20 15:19:20 +00:00
Roman Lebedev
63a71fba8d [InstCombine] Tests for (a+b)<=a && (a+b)!=0 fold (PR43259)
https://rise4fun.com/Alive/knp
https://rise4fun.com/Alive/ALap

llvm-svn: 372402
2019-09-20 15:06:47 +00:00
Oliver Cruickshank
7ea1afb2e4 [ARM] Fix CTTZ not generating correct instructions MVE
CTTZ intrinsic should have been set to Custom, not Expand

llvm-svn: 372401
2019-09-20 15:03:44 +00:00
Francesco Petrogalli
94323a35ed [docs] Remove training whitespaces. NFC
Subscribers: jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67835

llvm-svn: 372399
2019-09-20 15:02:32 +00:00
David Stenberg
fdb7370ebe Add a missing space in a MIR parser error message
llvm-svn: 372398
2019-09-20 14:41:41 +00:00
GN Sync Bot
a174c99253 gn build: Merge r372396
llvm-svn: 372397
2019-09-20 14:39:52 +00:00