Bill Wendling
b450d320ec
Encode the multi-load/store instructions with their respective modes ('ia',
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'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
Jim Grosbach
7aabb8c5ee
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
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llvm-svn: 119180
2010-11-15 20:47:07 +00:00
Jim Grosbach
a7676f5079
Nuke redundant encoding bit set.
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llvm-svn: 119164
2010-11-15 18:17:24 +00:00
Chris Lattner
b2daeac125
add fields to the .td files unconditionally, simplifying tblgen a bit.
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Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
Bill Wendling
49dd03e223
Comment out the defms until they're activated.
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llvm-svn: 119000
2010-11-13 11:20:05 +00:00
Bill Wendling
fadcb3cded
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
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llvm-svn: 118999
2010-11-13 10:57:02 +00:00
Bill Wendling
184bc1368d
Convert the modes to lower case.
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llvm-svn: 118998
2010-11-13 10:43:34 +00:00
Bill Wendling
0a55425158
Minor cleanups:
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- Get the opcode once.
- Add a ParserMatchClass to reglist.
llvm-svn: 118997
2010-11-13 10:40:19 +00:00
Bill Wendling
aa9ca6fcca
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
Evan Cheng
239d9b439d
Conditional moves are slightly more expensive than moves.
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llvm-svn: 118985
2010-11-13 05:14:20 +00:00
Evan Cheng
a7d3c3d387
Add conditional move of large immediate.
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llvm-svn: 118968
2010-11-13 02:25:14 +00:00
Jim Grosbach
cab8b12f7a
Swap multiclass operand order for consistency with other patterns.
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llvm-svn: 118965
2010-11-13 01:28:30 +00:00
Jim Grosbach
c8b3147ca5
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
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instructions.
llvm-svn: 118963
2010-11-13 01:07:20 +00:00
Jim Grosbach
03eb1993ea
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
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flag for the LDRT/STRT family instructions as a side effect.
llvm-svn: 118955
2010-11-13 00:35:48 +00:00
Evan Cheng
1f5296d832
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
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llvm-svn: 118945
2010-11-12 23:46:13 +00:00
Evan Cheng
f3c75f91e9
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
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llvm-svn: 118938
2010-11-12 23:03:38 +00:00
Evan Cheng
19f018a1be
Add conditional mvn instructions.
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llvm-svn: 118935
2010-11-12 22:42:47 +00:00
Jim Grosbach
e0ba69b81d
Zap a copy/paste-o bit of dead code.
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llvm-svn: 118926
2010-11-12 21:29:10 +00:00
Jim Grosbach
eaaf8294a5
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
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to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
Jim Grosbach
f9d1b45754
Fill in the default predication bits for ARM unconditional branch.
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llvm-svn: 118907
2010-11-12 18:13:26 +00:00
Jim Grosbach
cc8e5dc0c6
ARM fixup encoding for direct call instructions (BL).
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llvm-svn: 118829
2010-11-11 20:05:40 +00:00
Jim Grosbach
abf0e10ea0
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
Jim Grosbach
cfc32e3b5a
Encoding for ARM LDRSH_POST.
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llvm-svn: 118794
2010-11-11 16:55:29 +00:00
Jim Grosbach
8cb10f8def
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
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llvm-svn: 118767
2010-11-11 01:55:59 +00:00
Jim Grosbach
b86e183a33
Fix encoding of Ra register for ARM smla* instructions.
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llvm-svn: 118761
2010-11-11 01:27:41 +00:00
Jim Grosbach
3b13f9013c
ARM STRH encoding information.
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llvm-svn: 118757
2010-11-11 01:09:40 +00:00
Jim Grosbach
2c1d6373ab
Move LDM predicate operand encoding into base clase. Add STM missing STM
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encoding bits.
llvm-svn: 118738
2010-11-10 23:44:32 +00:00
Jim Grosbach
ad037e5ded
ARM LDM encoding for the mode (ia, ib, da, db) operand.
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llvm-svn: 118736
2010-11-10 23:38:36 +00:00
Jim Grosbach
ef95eee920
Fix ARM encoding of non-return LDM instructions.
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llvm-svn: 118732
2010-11-10 23:18:49 +00:00
Jim Grosbach
d832c84199
Fix ARM encoding of LDM+Return instruction.
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llvm-svn: 118730
2010-11-10 23:12:48 +00:00
Jim Grosbach
abe68922ca
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
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llvm-svn: 118600
2010-11-09 18:43:54 +00:00
Jim Grosbach
f64560f315
Add encoder method for ARM load/store shifted register offset operands.
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llvm-svn: 118513
2010-11-09 17:20:53 +00:00
Bill Wendling
41fb74d268
Revert r118457 and r118458. These won't hold for GPRs.
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llvm-svn: 118462
2010-11-09 00:30:18 +00:00
Bill Wendling
ab76e02a12
reglist has two operands.
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llvm-svn: 118457
2010-11-08 23:50:20 +00:00
Bill Wendling
19873cf3ff
Make RegList an ASM operand so that TableGen will generate code for it. This is
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an initial implementation and may change once reglists are fully fleshed out.
llvm-svn: 118390
2010-11-08 00:39:58 +00:00
Evan Cheng
165e65f53a
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
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llvm-svn: 118237
2010-11-04 05:19:35 +00:00
Evan Cheng
eab7251695
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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llvm-svn: 118160
2010-11-03 06:34:55 +00:00
Evan Cheng
b41703bc2f
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
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llvm-svn: 118152
2010-11-03 05:14:24 +00:00
Bill Wendling
34599f4aa8
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
Jim Grosbach
c10d3f3d4b
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
Chris Lattner
d3f7a5d3bd
Completely reject instructions that have an operand in their
...
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
Bill Wendling
1546322a9c
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
...
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
2010-11-02 22:31:46 +00:00
Owen Anderson
8aba4dbe03
Rename encoder methods to match naming convention.
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llvm-svn: 118093
2010-11-02 22:28:01 +00:00
Jim Grosbach
5fe61a5f86
Sort bit assignments. Cosmetic change only.
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llvm-svn: 118029
2010-11-02 17:59:04 +00:00
Owen Anderson
9d85c89ade
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
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llvm-svn: 117997
2010-11-02 01:24:55 +00:00
Owen Anderson
6647eb222b
Add correct NEON encodings for the "multiple single elements" form of vld.
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llvm-svn: 117984
2010-11-02 00:05:05 +00:00
Bob Wilson
411b511ac0
Add support for alignment operands on VLD1-lane instructions.
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This is another part of the fix for Radar 8599955.
llvm-svn: 117976
2010-11-01 23:40:51 +00:00
Jim Grosbach
76910aa62f
Mark ARM subtarget features that are available for the assembler.
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llvm-svn: 117929
2010-11-01 16:59:54 +00:00
Chris Lattner
01acd65875
reapply r117858 with apparent editor malfunction fixed (somehow I
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got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
Chris Lattner
8132a182e7
revert r117858 while I check out a failure I missed.
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llvm-svn: 117859
2010-10-31 19:05:32 +00:00