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Author SHA1 Message Date
Chris Lattner
70b05a5b88 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Bob Wilson
183c466006 Overhaul memory barriers in the ARM backend. Radar 8601999. 
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756
 2010-10-30 00:54:37 +00:00
Jim Grosbach
996d1280bd Encode the register list operands for ARM mode LDM/STM instructions. 
llvm-svn: 117753
 2010-10-30 00:37:59 +00:00
Jim Grosbach
7cf8dcc5bd s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand 
encoder functions.

llvm-svn: 117738
 2010-10-29 23:19:55 +00:00
Jim Grosbach
fcfc42b7bb Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
 2010-10-29 21:35:25 +00:00
Jim Grosbach
52638aa1c8 Fix typo. 
llvm-svn: 117703
 2010-10-29 20:21:49 +00:00
Jim Grosbach
4ca61d9877 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
llvm-svn: 117702
 2010-10-29 20:21:36 +00:00
Jim Grosbach
162e3345fb ARM mode LDREX*/STREX* binary encodings. 
llvm-svn: 117695
 2010-10-29 19:58:57 +00:00
Jim Grosbach
5bc94b46a9 Encoding information for ARM conditional move instructions. 
llvm-svn: 117687
 2010-10-29 19:28:17 +00:00
Chris Lattner
115cd02d22 add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Jim Grosbach
d02c1c7d77 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. 
llvm-svn: 117571
 2010-10-28 18:34:10 +00:00
Evan Cheng
bc4588c439 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng
fdc80a0316 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Evan Cheng
44d2802e1d Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Jim Grosbach
86ecfda983 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Owen Anderson
9437a20a72 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Jim Grosbach
0df1207e99 ARM JIT fix for LDRi12 and company. 
llvm-svn: 117478
 2010-10-27 19:55:59 +00:00
Jim Grosbach
4d4caf1384 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach
625e128d29 Since I parameterized this bit, I should probably actually use said parameter. 
llvm-svn: 117418
 2010-10-26 23:58:04 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Jim Grosbach
6d65ad0408 Trailing whitespace. 
llvm-svn: 117188
 2010-10-22 23:48:29 +00:00
Jim Grosbach
bba77cca02 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Jim Grosbach
10195e9b73 Add the encoding information for the rest of the ARM mode multiply instructions. 
llvm-svn: 117133
 2010-10-22 19:15:30 +00:00
Jim Grosbach
ca2897a0ca More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Jim Grosbach
eabb7c5bd1 Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

llvm-svn: 117114
 2010-10-22 17:42:06 +00:00
Jim Grosbach
0ae6bf8095 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
Jim Grosbach
d86073aa9a ARM binary encoding for some of the multiply instructions. 
llvm-svn: 117080
 2010-10-21 22:52:30 +00:00
Jim Grosbach
7c42142b71 ARM binary encodings for MVN variants. 
llvm-svn: 117076
 2010-10-21 22:19:32 +00:00
Jim Grosbach
cb41e97b5c ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Jim Grosbach
a8c0be5343 Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any 
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879
 2010-10-19 23:27:08 +00:00
Jim Grosbach
10fd33ecfc ARM encoding information for [SU]SAT* instructions. 
llvm-svn: 116768
 2010-10-18 23:35:38 +00:00
Jim Grosbach
5d7a5f8d33 Encoding information for the various ARM saturating add/sub instructions. 
llvm-svn: 116612
 2010-10-15 19:49:46 +00:00
Jim Grosbach
785858b2ba ARM binary encoding information for RSB and RSC instructions. 
llvm-svn: 116604
 2010-10-15 18:42:41 +00:00
Jim Grosbach
67f94c42d8 ARM mode encoding information for UBFX and SBFX instructions. 
llvm-svn: 116588
 2010-10-15 17:15:16 +00:00
Bob Wilson
6b6b53ad6f Remove unused ARMISD::AND selection DAG node. 
llvm-svn: 116566
 2010-10-15 04:34:40 +00:00
Jim Grosbach
b01bcbd047 Encoding info for extension instructions. 
llvm-svn: 116560
 2010-10-15 02:29:58 +00:00
Jim Grosbach
6da1b52d7b Add missing Rd encoding for MOVs instruction. 
llvm-svn: 116537
 2010-10-14 23:28:31 +00:00
Jim Grosbach
804505c7d4 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534
 2010-10-14 22:57:13 +00:00
Jim Grosbach
29dc23398f Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

llvm-svn: 116512
 2010-10-14 20:43:44 +00:00
Jim Grosbach
73c78f8790 MOVi16 and MOVT ARM mode encodings. 
llvm-svn: 116498
 2010-10-14 18:54:27 +00:00
Jim Grosbach
6d5cb39757 Simplify encoding information and add 'dst' operand info for TAILJMP. 
llvm-svn: 116488
 2010-10-14 17:24:28 +00:00
Jim Grosbach
41cd0dd4ba Add a FIXME. 
llvm-svn: 116449
 2010-10-13 22:55:33 +00:00
Jim Grosbach
4c80dbda49 Add operand encoding bits for SMC and SVC in ARM mode. 
llvm-svn: 116447
 2010-10-13 22:38:23 +00:00
Jim Grosbach
66822f70b8 More encoding cleanup. Also add register Rd operands for indirect branches. 
llvm-svn: 116444
 2010-10-13 22:09:34 +00:00
Jim Grosbach
630efeb050 Simplify some ARM encoding information. 
llvm-svn: 116440
 2010-10-13 21:48:54 +00:00
Jim Grosbach
f1d59d0fd5 Add a FIXME. The ADR instruction is a bit odd. 
llvm-svn: 116437
 2010-10-13 21:32:30 +00:00
Jim Grosbach
1699d40f80 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
 2010-10-13 21:00:04 +00:00
Jim Grosbach
3a4bfe4573 Add a FIXME. 
llvm-svn: 116428
 2010-10-13 20:38:04 +00:00
Jim Grosbach
d079fee8b1 Make a few more bits of some simple instructions explicit. nop, yield, wfe, 
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

llvm-svn: 116427
 2010-10-13 20:30:55 +00:00
Jim Grosbach
8f0bea85bf Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach
79156dadf2 Fix encoding for compares. No Rd register. 
llvm-svn: 116414
 2010-10-13 18:05:25 +00:00
Jim Grosbach
9c4a598ef2 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
llvm-svn: 116412
 2010-10-13 18:00:52 +00:00
Jim Grosbach
3fe0337063 Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

llvm-svn: 116384
 2010-10-13 00:50:27 +00:00
Jim Grosbach
79cebf409d Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377
 2010-10-12 23:53:58 +00:00
Jim Grosbach
de78ccb013 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367
 2010-10-12 23:18:08 +00:00
Jim Grosbach
a0f673b561 Add MOVi ARM encoding. 
llvm-svn: 116321
 2010-10-12 18:09:12 +00:00
Jim Grosbach
10d9bbe0ca Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

llvm-svn: 116313
 2010-10-12 17:11:26 +00:00
Jim Grosbach
29ef87e765 MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

llvm-svn: 116259
 2010-10-11 23:16:21 +00:00
Jim Grosbach
a697e32f36 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.

llvm-svn: 116213
 2010-10-11 18:51:51 +00:00
Jim Grosbach
3075d28c15 Implement a few more binary encoding bits. Still very early stage proof-of- 
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112
 2010-10-08 21:45:55 +00:00
Jim Grosbach
1e2566c20d Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. 
llvm-svn: 115884
 2010-10-07 00:42:42 +00:00
Jim Grosbach
de2bd8cd3f Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions. 
llvm-svn: 115853
 2010-10-06 22:01:26 +00:00
Jim Grosbach
4c7da8acbc Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). 
llvm-svn: 115845
 2010-10-06 21:36:43 +00:00
Evan Cheng
6fbb6dea7c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755
 2010-10-06 06:27:31 +00:00
Jim Grosbach
8440cebbe9 Nuke a bunch of no-longer-needed comment-only asm strings. 
llvm-svn: 115370
 2010-10-01 23:09:33 +00:00
Jim Grosbach
2bf1c488de Nuke a few more unused asm strings 
llvm-svn: 115193
 2010-09-30 19:53:58 +00:00
Jim Grosbach
52b5709c99 The asm strings are never used at all, so just nuke 'em entirely. 
llvm-svn: 115160
 2010-09-30 16:56:53 +00:00
Jim Grosbach
ad67153eb3 Go ahead and jump! 
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.

llvm-svn: 115130
 2010-09-30 02:18:06 +00:00
Evan Cheng
fa5d40dbff ARM instruction itinerary fixes: 
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

llvm-svn: 115121
 2010-09-30 01:08:25 +00:00
Jim Grosbach
fd8705ab4a Add specializations of addrmode2 that allow differentiating those forms 
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.

llvm-svn: 115066
 2010-09-29 19:03:54 +00:00
Evan Cheng
7eb08b1ad9 Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. 
llvm-svn: 115010
 2010-09-29 00:49:25 +00:00
Evan Cheng
7fffe3cf58 Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. 
llvm-svn: 115008
 2010-09-29 00:27:46 +00:00
Evan Cheng
64a24ab747 Fix zero and sign extension instructions scheduling itineraries. 
llvm-svn: 114780
 2010-09-25 00:49:35 +00:00
Evan Cheng
eb81dc39dc Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 
llvm-svn: 114766
 2010-09-24 22:03:46 +00:00
Owen Anderson
4fc55c0e02 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further 
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710
 2010-09-23 23:45:25 +00:00
Jim Grosbach
c6efcc192d #+4 --> #4 for consistency with other asm output 
llvm-svn: 114706
 2010-09-23 23:32:38 +00:00
Jim Grosbach
7bd79eb9e8 Fix formatting of output .s code 
llvm-svn: 114705
 2010-09-23 23:03:26 +00:00
Owen Anderson
15c6948d29 Add isConditionalMove bits to X86 and ARM instructions. 
llvm-svn: 114703
 2010-09-23 22:57:01 +00:00
Jim Grosbach
bcafcce601 Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't 
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.

llvm-svn: 114679
 2010-09-23 18:05:37 +00:00
Chris Lattner
55043ef46a fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471
 2010-09-21 20:31:19 +00:00
Bill Wendling
6cc7baa725 Reword since this may not be a bug but intended behavior. 
llvm-svn: 113584
 2010-09-10 10:31:11 +00:00
Evan Cheng
b87520ca74 Fix LDM_RET schedule itinery. 
llvm-svn: 113435
 2010-09-08 22:57:08 +00:00
Chris Lattner
b74759a9fa temporarily revert r112664, it is causing a decoding conflict, and 
the testcases should be merged.

llvm-svn: 112711
 2010-09-01 16:00:50 +00:00
Bill Wendling
bb6052cfd6 We have a chance for an optimization. Consider this code: 
int x(int t) {
  if (t & 256)
    return -26;
  return 0;
}

We generate this:

     tst.w   r0, #256
     mvn     r0, #25
     it      eq
     moveq   r0, #0

while gcc generates this:

     ands    r0, r0, #256
     it      ne
     mvnne   r0, #25
     bx      lr

Scandalous really!

During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):

  %r0 = ISD::AND ...
  ARMISD::CMPZ %r0, 0         @ sets [CPSR]
  %r0 = ARMISD::MOVCC 0, -26  @ reads [CPSR]

All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!

llvm-svn: 112664
 2010-08-31 22:41:22 +00:00
Bill Wendling
4a52e8fec0 And ANDS pattern to match the t2ANDS pattern. 
llvm-svn: 112654
 2010-08-31 22:05:37 +00:00
Jim Grosbach
674b25ce31 Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should 
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.

llvm-svn: 112503
 2010-08-30 19:49:58 +00:00
Bill Wendling
8a7258d771 Fix whitespaces. No functionality changes. 
llvm-svn: 112421
 2010-08-29 11:31:07 +00:00
Bill Wendling
6e586677a7 File missing from last commit. 
llvm-svn: 112394
 2010-08-29 03:02:28 +00:00
Bill Wendling
c76a3e317c Reapply r112176 without removing the other CMN patterns (that was unintentional). 
llvm-svn: 112206
 2010-08-26 18:33:51 +00:00
Jakob Stoklund Olesen
20dbe1681b Don't call tablegen'ed Predicate_* functions in the ARM target. 
llvm-svn: 111277
 2010-08-17 20:39:04 +00:00
Jim Grosbach
1d9631950f 80 column cleanup. 
llvm-svn: 111266
 2010-08-17 18:39:16 +00:00
Bob Wilson
e382fce916 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251
 2010-08-17 17:23:19 +00:00
Bob Wilson
d662e8cd02 Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee 
that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196
 2010-08-16 22:26:55 +00:00
Bob Wilson
985dab611d Rename sat_shift operand to shift_imm, in preparation for using it for other 
instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168
 2010-08-16 18:27:34 +00:00
Bob Wilson
98641e5a51 Remove unused code. 
llvm-svn: 111154
 2010-08-16 17:06:03 +00:00
Johnny Chen
78345b1dfe Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951
 2010-08-12 20:46:17 +00:00
Johnny Chen
9a37d16281 Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.

llvm-svn: 110880
 2010-08-11 23:35:12 +00:00
Bob Wilson
3582107cf8 Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Evan Cheng
e67c4c3723 Really control isel of barrier instructions with cpu feature. 
llvm-svn: 110787
 2010-08-11 06:36:31 +00:00