Evan Cheng
0c445855f2
Number of NodeTypes now exceeds 128.
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llvm-svn: 26503
2006-03-03 06:58:59 +00:00
Chris Lattner
40501a50fe
Add interfaces for targets to provide target-specific dag combiner optimizations.
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llvm-svn: 26442
2006-03-01 04:52:55 +00:00
Evan Cheng
b8a44ab1dd
Missing a cast previously.
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llvm-svn: 26434
2006-03-01 00:58:54 +00:00
Chris Lattner
0957a2e87c
Add C_Memory operand type
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llvm-svn: 26344
2006-02-24 01:10:14 +00:00
Evan Cheng
305141c1ba
- Added option -relocation-model to set relocation model. Valid values include static, pic,
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dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
llvm-svn: 26315
2006-02-22 20:19:42 +00:00
Chris Lattner
ed45ad33b7
Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean.
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Patch by Martin Partel!
llvm-svn: 26313
2006-02-22 16:23:43 +00:00
Chris Lattner
6bb2c3e9cd
split register class handling from explicit physreg handling.
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llvm-svn: 26308
2006-02-22 00:56:39 +00:00
Chris Lattner
086fd0f862
expose the set of values types holdable in a regclass to clients
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llvm-svn: 26307
2006-02-21 23:51:58 +00:00
Chris Lattner
ed3b59056a
Pass in a value type to getRegForInlineAsmConstraint, allowing targets to
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select different sets of registers depending on the type requested.
llvm-svn: 26304
2006-02-21 23:10:29 +00:00
Evan Cheng
bba9078fed
Move PICEnabled declaration here.
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llvm-svn: 26271
2006-02-18 00:06:03 +00:00
Nate Begeman
aef186befc
Fix a nit sabre noticed
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llvm-svn: 26262
2006-02-17 18:06:19 +00:00
Nate Begeman
0bc71999b9
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
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and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
Evan Cheng
f6c74c0096
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
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llvm-svn: 26174
2006-02-14 08:38:30 +00:00
Chris Lattner
478eb50b79
getConstraintType should be virtual.
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llvm-svn: 26041
2006-02-07 20:13:44 +00:00
Chris Lattner
2395722dbd
Add some methods for inline asm support.
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llvm-svn: 25950
2006-02-04 02:12:09 +00:00
Nate Begeman
2d9838ec9b
Add a framework for eliminating instructions that produces undemanded bits.
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llvm-svn: 25945
2006-02-03 22:24:05 +00:00
Chris Lattner
6684ba101f
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,
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a far more logical place. Other methods should also be moved if anyone
is interested. :)
llvm-svn: 25912
2006-02-02 20:11:55 +00:00
Chris Lattner
3cbf670f57
add a new isStoreToStackSlot method
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llvm-svn: 25909
2006-02-02 19:55:29 +00:00
Chris Lattner
5583b2e227
Clear the OpAction field before setting it. This allows a target to set
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an instruction operation action to Expand, then set it to Legal later.
llvm-svn: 25812
2006-01-30 06:09:03 +00:00
Chris Lattner
a1cc69e24e
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,
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making isMaskedValueZeroForTargetNode simpler, and useable from other parts
of the compiler.
llvm-svn: 25802
2006-01-30 04:08:18 +00:00
Chris Lattner
7f64ff5ce0
Pass the address of the main MaskedValueIsZero function to allow recursion.
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llvm-svn: 25797
2006-01-30 03:48:36 +00:00
Chris Lattner
a8ca8f5eb9
Clean up the interface to ValueTypeActions, allowing Legalize to use a copy
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of it more cleanly. Double the size of OpActions, allowing it to hold actions
for any VT.
llvm-svn: 25782
2006-01-29 08:40:37 +00:00
Chris Lattner
2240c0df71
remove this method I just added, now is not the time.
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llvm-svn: 25729
2006-01-28 03:43:33 +00:00
Chris Lattner
063c13029b
add a new callback
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llvm-svn: 25727
2006-01-28 03:37:03 +00:00
Nate Begeman
87c2c0e66b
Implement Promote for VAARG, and allow it to be custom promoted for people
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who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
Nate Begeman
d2c6fbef4a
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
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the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
Chris Lattner
b234392bc5
Add a common INLINEASM opcode
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llvm-svn: 25667
2006-01-26 23:27:02 +00:00
Jeff Cohen
f329a41a66
Improve compatibility with VC2005, patch by Morten Ofstad!
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llvm-svn: 25661
2006-01-26 20:41:32 +00:00
Chris Lattner
ab8e0e40f9
Add a method for inline asm support.
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llvm-svn: 25656
2006-01-26 20:27:33 +00:00
Nate Begeman
c29fac7fce
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
Evan Cheng
f4b53efbb2
Add a enum to specify target scheduling preference: SchedulingForLatency or
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SchedulingForRegPressure. Added corresponding methods to set / get the value.
llvm-svn: 25598
2006-01-25 09:09:02 +00:00
Chris Lattner
b64d2919c7
Add a new InvalidateStructLayoutInfo method and some comments.
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llvm-svn: 25303
2006-01-14 00:06:42 +00:00
Chris Lattner
8fe9dd16fb
Provide an interface for Targets to specify their stack pointer register
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for llvm.stacksave/restore.
llvm-svn: 25275
2006-01-13 17:47:52 +00:00
Jeff Cohen
8727139340
Oh oh... Unix is case sensitive.
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llvm-svn: 24928
2005-12-22 01:46:59 +00:00
Jeff Cohen
8afabfd8f1
Make it compile with VC++.
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llvm-svn: 24927
2005-12-22 01:44:51 +00:00
Evan Cheng
822f360f84
Added TargetLowering::isMaskedValueZeroForTargetNode() declaration.
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llvm-svn: 24923
2005-12-21 23:15:41 +00:00
Evan Cheng
44e4e6a57f
Added a hook to print out names of target specific DAG nodes.
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llvm-svn: 24877
2005-12-20 06:22:03 +00:00
Nate Begeman
811a41a87c
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
Nate Begeman
a1c2df2471
Add the majority of the vector machien value types we expect to support,
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and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
Nate Begeman
5784fb4adf
Teach the type lowering code about turning packed types into vector types.
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Next step: generating vector dag nodes, and legalizing them into scalar
code.
llvm-svn: 24404
2005-11-17 21:44:42 +00:00
Chris Lattner
bb448515ae
Add a new option to indicate we want the code generator to emit code quickly,
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not spending tons of time microoptimizing it. This is useful for an -O0
style of build.
llvm-svn: 24235
2005-11-08 02:12:47 +00:00
Jeff Cohen
16669485c1
<cassert> no longer required to make VC++ happy.
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llvm-svn: 24177
2005-11-04 02:59:16 +00:00
Duraid Madina
feeaabd6f1
change NULL to 0, unbreaks the ppc target when building on ia64
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llvm-svn: 24176
2005-11-04 01:45:04 +00:00
Jim Laskey
42681c1d58
1. Remove ranges from itinerary data.
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2. Tidy up the subtarget emittined code.
llvm-svn: 24172
2005-11-03 22:47:41 +00:00
Jeff Cohen
ae39880d3a
Keep VC++ happy.
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llvm-svn: 24148
2005-11-02 04:03:16 +00:00
Jim Laskey
4cb1e29b27
Allow itineraries to be passed through the Target Machine.
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llvm-svn: 24139
2005-11-01 20:06:59 +00:00
Jim Laskey
03f8b2a366
Structures used to hold scheduling information.
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llvm-svn: 24049
2005-10-27 18:18:05 +00:00
Jim Laskey
b377b32a58
Preparation of supporting scheduling info. Need to find info based on selected
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CPU.
llvm-svn: 23974
2005-10-25 15:15:28 +00:00
Chris Lattner
79ea8acebc
Move static functions to .cpp file, reduce #includes, pass strings by
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const&.
llvm-svn: 23890
2005-10-23 05:25:19 +00:00
Nate Begeman
6c42f509bc
Invert the TargetLowering flag that controls divide by consant expansion.
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Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
llvm-svn: 23853
2005-10-21 00:02:42 +00:00