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Commit Graph

14235 Commits

Author SHA1 Message Date
Chris Lattner
6632283a47 now that Type::getDescription() is dead, the TypePrinting class can move from Assembly/Writer.h to being
a private class in AsmWriter.cpp.

llvm-svn: 133361
2011-06-18 21:23:04 +00:00
Chris Lattner
50b274b1cb eliminate the Type::getDescription() method, using "<<" instead. This
removes some gunk from LLVMContext.

llvm-svn: 133360
2011-06-18 21:18:23 +00:00
Chris Lattner
db3efb92c5 improve some comments.
llvm-svn: 133359
2011-06-18 21:02:49 +00:00
Benjamin Kramer
0b4d4ce7c1 Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.
llvm-svn: 133348
2011-06-18 13:13:44 +00:00
Jakob Stoklund Olesen
d446052d33 Remove MethodProtos/MethodBodies and allocation_order_begin/end.
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.

The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.

It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.

llvm-svn: 133332
2011-06-18 03:08:20 +00:00
Jakob Stoklund Olesen
5da811d840 Provide AltOrders for specifying alternative allocation orders.
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.

This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.

llvm-svn: 133320
2011-06-18 00:50:49 +00:00
Bill Wendling
1d4e48661b Use the verbose asm flag instead of a new flag for decoding the LSDA.
llvm-svn: 133292
2011-06-17 20:55:01 +00:00
Nadav Rotem
0cec5ab356 Fix a bug in the type-lowering of integer-promoted elements. Add a check that
the newly created simple type is valid before checking its legality.
Re-commit the test file.

llvm-svn: 133291
2011-06-17 20:54:12 +00:00
Eric Christopher
25aa04466a Lower multiply with overflow checking to __mulo<mode>
calls if we haven't been able to lower them any
other way.

Fixes rdar://9090077 and rdar://9210061

llvm-svn: 133288
2011-06-17 20:41:29 +00:00
Bill Wendling
88bb5d74ab Add an option that allows one to "decode" the LSDA.
The LSDA is a bit difficult for the non-initiated to read. Even with comments,
it's not always clear what's going on. This wraps the ASM streamer in a class
that retains the LSDA and then emits a human-readable description of what's
going on in it.

So instead of having to make sense of:

Lexception1:
        .byte   255
        .byte   155
        .byte   168
        .space  1
        .byte   3
        .byte   26
Lset0 = Ltmp7-Leh_func_begin1
      .long     Lset0
Lset1 = Ltmp812-Ltmp7
      .long     Lset1
Lset2 = Ltmp913-Leh_func_begin1
      .long     Lset2
      .byte     3
Lset3 = Ltmp812-Leh_func_begin1
      .long     Lset3
Lset4 = Leh_func_end1-Ltmp812
      .long     Lset4
      .long     0
      .byte     0
      .byte     1
      .byte     0
      .byte     2
      .byte     125
      .long     __ZTIi@GOTPCREL+4
      .long     __ZTIPKc@GOTPCREL+4

you can read this instead:

## Exception Handling Table: Lexception1
##  @LPStart Encoding: omit
##    @TType Encoding: indirect pcrel sdata4
##        @TType Base: 40 bytes
## @CallSite Encoding: udata4
## @Action Table Size: 26 bytes

## Action 1:
##   A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception.
##     For type(s):  __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4
## Action 2:
##   A throw between Ltmp812 and Leh_func_end1 does not have a landing pad.

llvm-svn: 133286
2011-06-17 20:35:21 +00:00
Chris Lattner
dd6d168c92 Drop the "2" suffix on some enums.
llvm-svn: 133274
2011-06-17 18:17:37 +00:00
Chris Lattner
04d8431b16 remove support for a bunch of obsolete instruction encodings
and other backward compatibility hacks.

llvm-svn: 133273
2011-06-17 18:09:11 +00:00
Chris Lattner
d59a556c3a Remove some "2" suffixes from the metadata enums now that "1" is gone.
llvm-svn: 133269
2011-06-17 17:50:30 +00:00
Chris Lattner
c7bf0d0128 remove bitcode reader support for LLVM 2.7 metadata encoding.
llvm-svn: 133268
2011-06-17 17:48:53 +00:00
Lang Hames
20552cda1a Add a hook for PBQP clients to run a custom pre-alloc pass to run prior to PBQP allocation. Patch by Arnaud Allard de Grandmaison.
llvm-svn: 133249
2011-06-17 07:09:01 +00:00
Jakob Stoklund Olesen
c185689b5c Rename TRI::getAllocationOrder() to getRawAllocationOrder().
Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.

The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.

llvm-svn: 133216
2011-06-16 23:31:16 +00:00
Chris Lattner
59d895657b forward declare GraphTraits in Type.h instead of #includ'ing it.
llvm-svn: 133201
2011-06-16 21:49:23 +00:00
Chris Lattner
024b713434 change Type.h to forward declare ArrayRef instead of #including it.
llvm-svn: 133197
2011-06-16 21:37:15 +00:00
Chris Lattner
b235992acc move the address space into the subclass data field, saving a word on PointerType.
This limits the # address spaces to 2^23, which should be good enough.

llvm-svn: 133192
2011-06-16 21:17:17 +00:00
Chris Lattner
e266e33a4b tidy up some comments, store the 'isvararg' bit for FunctionType in
the SubclassData field, saving a word.

llvm-svn: 133191
2011-06-16 21:08:21 +00:00
Chris Lattner
1c22baaf6c remove Type::getVAArgsPromotedType, which is dead, and tidy up a bit.
llvm-svn: 133190
2011-06-16 21:00:43 +00:00
Jakub Staszak
5c7b7d64ba Introduce MachineBranchProbabilityInfo class, which has similar API to
BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184
2011-06-16 20:22:37 +00:00
Owen Anderson
c79aec8247 Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.

llvm-svn: 133178
2011-06-16 18:17:13 +00:00
Jakob Stoklund Olesen
3bf75a3861 Add TargetRegisterInfo::getRawAllocationOrder().
This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.

Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.

llvm-svn: 133170
2011-06-16 17:42:25 +00:00
Owen Anderson
a9bf21548f Fix formatting.
llvm-svn: 133164
2011-06-16 16:52:24 +00:00
John McCall
519c63cdeb The ARC language-specific optimizer. Credit to Dan Gohman.
llvm-svn: 133108
2011-06-15 23:37:01 +00:00
Owen Anderson
f98c2ea49d Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
llvm-svn: 133106
2011-06-15 23:35:18 +00:00
Jakob Stoklund Olesen
d89900e14c Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105
2011-06-15 23:28:14 +00:00
John McCall
e6835ee44e Add a new function attribute, nonlazybind, which inhibits lazy-loading
optimizations when emitting calls to the function;  instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call.  This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.

Currently only implemented for x86-64, where it turns into a call through
the global offset table.

Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.

llvm-svn: 133080
2011-06-15 20:36:13 +00:00
Eli Friedman
33a3b6d488 Remove unused code.
llvm-svn: 133078
2011-06-15 19:58:09 +00:00
Argyrios Kyrtzidis
81d5aec961 Constify PackedVector::reference::operator T().
llvm-svn: 133074
2011-06-15 19:18:13 +00:00
Jim Grosbach
2ec534dffe Diagnostic for undefined assembler local symbols.
Re-apply 133010, with fixes for inline assembler.

Original commit message:
"When an assembler local symbol is used but not defined in a module, a
Darwin assembler wants to issue a diagnostic to that effect."

Added fix to only perform the check when finalizing, as otherwise we're not
done and undefined symbols may simply not have been encountered yet.

Passes "make check" and a self-host check on Darwin.

llvm-svn: 133071
2011-06-15 18:33:28 +00:00
Andrew Trick
ce93f28a36 Added -stress-sched flag in the Asserts build.
Added a test case for handling physreg aliases during pre-RA-sched.

llvm-svn: 133063
2011-06-15 17:16:12 +00:00
Owen Anderson
e1cebd9e2e Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists.
At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries.  Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan.
With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time.  It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables.

llvm-svn: 133051
2011-06-15 06:53:50 +00:00
Ted Kremenek
947d9a7e53 add option for literal formatting to APInt::toString()
toString() now takes an optional bool argument that,
depending on the radix, adds the appropriate prefix
to the integer's string representation that makes it into a
meaningful C literal, e.g.:

hexademical: '-f' becomes '-0xf'
octal: '77' becomes '077'
binary: '110' becomes '0b110'

Patch by nobled@dreamwidth.org!

llvm-svn: 133032
2011-06-15 00:51:55 +00:00
Eli Friedman
47b3cd9fff Add "unknown" results for memdep, which mean "I don't know whether a dependence for the given instruction exists in the given block". This cleans up all the existing hacks in memdep which represent this concept by returning clobber with various unrelated instructions.
llvm-svn: 133031
2011-06-15 00:47:34 +00:00
Jim Grosbach
e5f4cecf01 Revert 133010. Self-hosted buildbot unhappy.
Apparently llvm itself generates undefined assembler local labels, causing
self-hosting problems with this patch. Reverting until that's sorted out.

llvm-svn: 133013
2011-06-14 21:51:20 +00:00
Jim Grosbach
596a1b7d98 Diagnostic for undefined assembler local symbols.
When an assembler local symbol is used but not defined in a module, a
Darwin assembler wants to issue a diagnostic to that effect.

rdar://9559714

llvm-svn: 133010
2011-06-14 21:13:25 +00:00
Bruno Cardoso Lopes
b6afc5168f Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

llvm-svn: 132976
2011-06-14 04:58:37 +00:00
Benjamin Kramer
8bd126a5c6 Revert r132910 and r132909 on behalf of Michael. They didn't build with clang.
llvm-svn: 132914
2011-06-13 12:56:51 +00:00
Michael J. Spencer
8288453980 Revert the last two commits in the series. r132911, r132912.
llvm-svn: 132913
2011-06-13 11:53:31 +00:00
Michael J. Spencer
642af05937 Make Binary the parent of ObjectFile and update children to new interface.
llvm-svn: 132911
2011-06-13 11:12:33 +00:00
Michael J. Spencer
bc30ca9794 Add Binary class. This is a cleaner parent than ObjectFile.
llvm-svn: 132910
2011-06-13 11:12:12 +00:00
Michael J. Spencer
d6178b9f59 Add Object/Error.
llvm-svn: 132909
2011-06-13 11:11:59 +00:00
Michael J. Spencer
39a329f72f Fix spelling and sort CMakeLists.txt.
llvm-svn: 132908
2011-06-13 11:11:39 +00:00
Nadav Rotem
1086d5acda Bugfix: When looking for a legal vector type, stop looking when a non-simple
element type is found.
This fix addresses some of the tests in Duncan's testcase (forthcoming).

llvm-svn: 132891
2011-06-12 14:40:30 +00:00
Jakob Stoklund Olesen
4c1c395789 Tweak hash function and compress hash tables.
Make the hash tables as small as possible while ensuring that all
lookups can be done in less than 8 probes.

Cut the aliases hash table in half by only storing a < b pairs - it
is a symmetric relation.

Use larger multipliers on the initial hash function to ensure that it
properly covers the whole table, and to resolve some clustering in the
very regular ARM register bank.

This reduces the size of most of these tables by 4x - 8x. For instance,
the ARM tables shrink from 48 KB to 8 KB.

llvm-svn: 132888
2011-06-12 07:04:32 +00:00
Jakob Stoklund Olesen
7d0e28c893 Compute lists of sub-regs, super-regs, and overlapping regs.
Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:

- Sub-register lists come from a pre-order traversal of the graph
  defined by the SubRegs lists in the .td files.

- Super-register lists are topologically ordered so no register comes
  before any of its sub-registers. When the sub-register graph is not a
  tree, independent super-registers appear in numerical order.

- Lists of overlapping registers are ordered according to register
  number.

This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.

The old computations are still there, but will be removed shortly.

llvm-svn: 132881
2011-06-12 03:05:52 +00:00
Bill Wendling
0f5a6fb66c Reformatting. Moving class definitions to more natural places. No functionalogical changes.
llvm-svn: 132876
2011-06-11 11:37:49 +00:00
Andrew Trick
4591f882c2 Branch profiling: floating-point avoidance.
Patch by: Jakub Staszak!

Introduces BranchProbability. Changes unsigned to uint32_t all over and
uint64_t only when overflow is expected.

llvm-svn: 132867
2011-06-11 01:05:22 +00:00