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Commit Graph

190082 Commits

Author SHA1 Message Date
Andrew Wei
a5ebce551b [LegalizeTypes] Add SoftenFloatResult support for STRICT_SINT_TO_FP/STRICT_UINT_TO_FP
Some target like arm/riscv with soft-float will have compiling crash when using -fno-unsafe-math-optimization option.
This patch will add the missing strict FP support to SoftenFloatRes_XINT_TO_FP.

Differential Revision: https://reviews.llvm.org/D72277
2020-01-14 01:01:56 +08:00
Simon Pilgrim
fe2531a3c7 [SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() ISD::SRA support
Allows us to handle more non-uniform SRA sign bits cases
2020-01-13 16:55:02 +00:00
Simon Pilgrim
e5d411f28d [X86][SSE] Add sitofp(ashr(x,y)) test case with non-uniform shift value 2020-01-13 16:55:02 +00:00
Simon Pilgrim
708a2570bc [X86] Add AVX2 known signbits codegen tests 2020-01-13 16:55:01 +00:00
David Green
d50acf0671 [Scheduler] Remove superfluous casts. NFC 2020-01-13 16:34:13 +00:00
Danilo Carvalho Grael
b5209f057d [AArch64][SVE] Add patterns for some arith SVE instructions.
Summary: Add patterns for the following instructions:
- smax, smin, umax, umin

Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim, kmclaughlin

Subscribers: amehsan

Differential Revision: https://reviews.llvm.org/D71779
2020-01-13 11:39:42 -05:00
Teresa Johnson
85d0c68d2a [ThinLTO] Add additional ThinLTO pipeline testing with new PM
Summary:
I've added some more extensive ThinLTO pipeline testing with the new PM,
motivated by the bug fixed in D72386.

I beefed up llvm/test/Other/new-pm-pgo.ll a little so that it tests
ThinLTO pre and post link with PGO, similar to the testing for the
default pipelines with PGO.

Added new pre and post link PGO tests for both instrumentation and
sample PGO that exhaustively test the pipelines at different
optimization levels via opt.

Added a clang test to exhaustively test the post link pipeline invoked for
distributed builds. I am currently only testing O2 and O3 since these
are the most important for performance.

It would be nice to add similar exhaustive testing for full LTO, and for
the old PM, but I don't have the bandwidth now and this is a start to
cover some of the situations that are not currently default and were
under tested.

Reviewers: wmi

Subscribers: mehdi_amini, inglorion, hiraditya, steven_wu, dexonsmith, jfb, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D72538
2020-01-13 08:29:56 -08:00
James Henderson
69703dcf78 [DebugInfo] Make debug line address size mismatch non-fatal to parsing
Reasonable assumptions can be made when a parsed address length does not
match the expected length, so there's no need for this to be fatal.

Reviewed by: ikudrin

Differential Revision: https://reviews.llvm.org/D72154
2020-01-13 16:27:05 +00:00
Kazu Hirata
e884b78242 [Inlining] Add PreInlineThreshold for the new pass manager
Summary:
This patch makes it easy to try out different preinlining thresholds
with a command-line switch just like -preinline-threshold for the
legacy pass manager.

Reviewers: davidxl

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72618
2020-01-13 07:59:42 -08:00
Luís Marques
cca8a4fe6c [RISCV] Handle globals and block addresses in asm operands
Summary: These seem to be the machine operand types currently needed by the
RISC-V target.

Reviewers: asb, lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72275
2020-01-13 15:34:56 +00:00
Sam McCall
a144c53cb3 Add missing triples to tests in 0c29d3ff2233696f663ae34a8aeda23c750ac68f so they target the right arch. 2020-01-13 15:58:49 +01:00
Pablo Barrio
025fa2bbb5 [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below
Summary:
The Pointer Authentication Extension (PAC) was added in Armv8.3-A. Some
instructions are implemented in the HINT space to allow compiling code
common to CPUs regardless of whether they feature PAC or not, and still
benefit from PAC protection in the PAC-enabled CPUs.

The 8.3-specific mnemonics were currently enabled in any architecture, and
LLVM was emitting them in assembly files when PAC code generation was
enabled. This was ok for compilations where both LLVM codegen and the
integrated assembler were used. However, the LLVM codegen was not
compatible with other assemblers (e.g. GAS). Given the fact that the
approach from these assemblers (i.e. to disallow Armv8.3-A mnemonics if
compiling for Armv8.2-A or lower) is entirely reasonable, this patch makes
LLVM to emit HINT when building for Armv8.2-A and below, instead of
PACIASP, AUTIASP and friends. Then, LLVM assembly should be compatible
with other assemblers.

Reviewers: samparker, chill, LukeCheeseman

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71658
2020-01-13 14:14:48 +00:00
Alex Richardson
94c22c4d69 [MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbols
The R_(MICRO)MIPS_JALR optimization only works when used against functions.
Using the relocation against a data symbol (e.g. function pointer) will
cause some linkers that don't ignore the hint in this case (e.g. LLD prior
to commit 5bab291b7b) to generate a relative branch to the data symbol
which crashes at run time. Before this patch, LLVM was erroneously emitting
these relocations against local-dynamic TLS function pointers and global
function pointers with internal visibility.

Reviewers: atanasyan, jrtc27, vstefanovic
Reviewed By: atanasyan
Differential Revision: https://reviews.llvm.org/D72571
2020-01-13 14:14:03 +00:00
Alex Richardson
53f757e913 [MIPS][ELF] Use PC-relative relocations in .eh_frame when possible
When compiling position-independent executables, we now use
DW_EH_PE_pcrel | DW_EH_PE_sdata4. However, the MIPS ABI does not define a
64-bit PC-relative ELF relocation so we cannot use sdata8 for the large
code model case. When using the large code model, we fall back to the
previous behaviour of generating absolute relocations.

With this change clang-generated .o files can be linked by LLD without
having to pass -Wl,-z,notext (which creates text relocations).
This is simpler than the approach used by ld.bfd, which rewrites the
.eh_frame section to convert absolute relocations into relative references.

I saw in D13104 that apparently ld.bfd did not accept pc-relative relocations
for MIPS ouput at some point. However, I also checked that recent ld.bfd
can process the clang-generated .o files so this no longer seems true.

Reviewed By: atanasyan
Differential Revision: https://reviews.llvm.org/D72228
2020-01-13 14:14:03 +00:00
Sanjay Patel
03ef20d9a0 [InstSimplify] move tests for select from InstCombine; NFC
InstCombine has transforms that would enable these simplifications
in an indirect way, but those transforms are unsafe and likely to
be removed.
2020-01-13 09:13:21 -05:00
Simon Pilgrim
42948f9f44 [SelectionDAG] ComputeNumSignBits - Use getValidShiftAmountConstant for shift opcodes
getValidShiftAmountConstant handles out of bounds shift amounts for us, allowing us to remove the local handling.
2020-01-13 14:12:12 +00:00
Simon Pilgrim
5bd29598ab [SelectionDAG] ComputeKnownBits - Add DemandedElts support to getValidShiftAmountConstant/getValidMinimumShiftAmountConstant() 2020-01-13 14:12:12 +00:00
Simon Pilgrim
cddab58467 [X86] Add knownbits tests showing missing shift amount demanded elts handling. 2020-01-13 14:12:12 +00:00
Ulrich Weigand
de4e3874c1 [FPEnv] Fix chain handling for fpexcept.strict nodes
We need to ensure that fpexcept.strict nodes are not optimized away even if
the result is unused. To do that, we need to chain them into the block's
terminator nodes, like already done for PendingExcepts.

This patch adds two new lists of pending chains, PendingConstrainedFP and
PendingConstrainedFPStrict to hold constrained FP intrinsic nodes without
and with fpexcept.strict markers. This allows not only to solve the above
problem, but also to relax chains a bit further by no longer flushing all
FP nodes before a store or other memory access. (They are still flushed
before nodes with other side effects.)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D72341
2020-01-13 14:38:49 +01:00
Matt Arsenault
c79fe07152 GlobalISel: Fix assertion on wide G_ZEXT sources
It's possible to have a type that needs a mask greater than 64-bits.
2020-01-13 08:29:45 -05:00
Miloš Stojanović
fc69928868 [llvm-exegesis] Remove unneeded std::move()
Caught by buildbot breakage:

/home/docker/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp:89:12: error: moving a local object in a return statement prevents copy elision [-Werror,-Wpessimizing-move]
    return std::move(Instructions);
           ^
/home/docker/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp:89:12: note: remove std::move call here
    return std::move(Instructions);
           ^~~~~~~~~~            ~
2020-01-13 14:19:17 +01:00
Simon Pilgrim
484860de99 [SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD::SHL support
As mentioned on D72573
2020-01-13 12:02:13 +00:00
Simon Pilgrim
96b2d1c612 [X86][SSE] Add knownbits test showing missing getValidMinimumShiftAmountConstant() ISD::SHL support
As mentioned on D72573
2020-01-13 12:02:13 +00:00
Miloš Stojanović
7696c3e850 [llvm-exegesis][mips] Expand loadImmediate()
Add support for loading 32-bit immediates and enable the use of GPR64
registers.

Differential Revision: https://reviews.llvm.org/D71873
2020-01-13 12:32:13 +01:00
Simon Pilgrim
5554f90776 [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)
As detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value.

This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits.

Differential Revision: https://reviews.llvm.org/D72573
2020-01-13 11:08:12 +00:00
Simon Pilgrim
340feeb91b [X86] Fix MSVC "truncation from 'int' to 'bool'" warning. NFCI. 2020-01-13 11:08:12 +00:00
James Henderson
a5ce9c1527 [DebugInfo][Support] Replace DWARFDataExtractor size function
This patch adds a new size function to the base DataExtractor class,
which removes the need for the DWARFDataExtractor size function.

It is unclear why DWARFDataExtractor's size function returned zero in
some circumstances (i.e. when it is constructed without a section, and
with a different data source instead), so that behaviour has changed.
The old behaviour could cause an assertion in the debug line parser, as
the size did not reflect the actual data available, and could be lower
than the current offset being parsed.

Reviewed by: dblaikie

Differential Revision: https://reviews.llvm.org/D72337
2020-01-13 10:53:00 +00:00
Sjoerd Meijer
2adc803d9d ARMLowOverheadLoops: return earlier to avoid printing irrelevant dbg msg. NFC 2020-01-13 10:24:10 +00:00
KAWASHIMA Takahiro
78130ba3e6 This option allows selecting the TLS size in the local exec TLS model,
which is the default TLS model for non-PIC objects. This allows large/
many thread local variables or a compact/fast code in an executable.

Specification is same as that of GCC. For example, the code model
option precedes the TLS size option.

TLS access models other than local-exec are not changed. It means
supoort of the large code model is only in the local exec TLS model.

Patch By KAWASHIMA Takahiro (kawashima-fj <t-kawashima@fujitsu.com>)
Reviewers: dmgreen, mstorsjo, t.p.northover, peter.smith, ostannard
Reviewd By: peter.smith
Committed by: peter.smith

Differential Revision: https://reviews.llvm.org/D71688
2020-01-13 10:16:53 +00:00
Sam Elliott
4897d2be46 [RISCV] Collect Statistics on Compressed Instructions
Summary:
It is useful to keep statistics on how many instructions we have
compressed, so we can see if future changes are increasing or decreasing this
number.

Reviewers: asb, luismarques

Reviewed By: asb, luismarques

Subscribers: xbolva00, sameer.abuasal, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67495
2020-01-13 10:04:05 +00:00
Sam Parker
34a68258ae [NFC] Update loop.decrement.reg intrinsic comment
Note that the intrinsic is now understood by SCEV and that other
optimisations can treat it as a sub.
2020-01-13 09:18:57 +00:00
Sjoerd Meijer
374875f92a [SCEV] Follow up of D71563: addressing post commit comment. NFC. 2020-01-13 08:54:38 +00:00
Awanish Pandey
385e6ab82f [DWARF5][DebugInfo]: Added support for DebugInfo generation for auto return type for C++ member functions.
Summary:
This patch will provide support for auto return type for the C++ member
functions. Before this return type of the member function is deduced and
stored in the DIE.
This patch includes llvm side implementation of this feature.

Patch by: Awanish Pandey <Awanish.Pandey@amd.com>

Reviewers: dblaikie, aprantl, shafik, alok, SouraVX, jini.susan.george

Reviewed by: dblaikie

Differential Revision: https://reviews.llvm.org/D70524
2020-01-13 12:26:13 +05:30
Craig Topper
20ba23ae6a [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes.
At least one of these is used without a Glue. This doesn't seem
to change the X86GenDAGISel.inc output so maybe it doesn't matter?
2020-01-12 21:11:18 -08:00
Matt Arsenault
6c67abdba0 AMDGPU: Split test function
This avoids slightly different scheduling/regalloc behavior, and
avoids a test diff between GlobalISel and SelectionDAG.
2020-01-12 22:44:51 -05:00
Matt Arsenault
bab10482dd AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
We don't use the xexec register classes for arbitrary values
anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-12 22:44:51 -05:00
Matt Arsenault
3a13f0680f AMDGPU/GlobalISel: Copy type when inserting readfirstlane
getDefIgnoringCopies will fail to find any def if no type is set if we
try to use it on the use's operand, so propagate the type.
2020-01-12 22:44:51 -05:00
Zheng Chen
d8d9e920a8 [SCEV] accurate range for addrecexpr with nuw flag
If addrecexpr has nuw flag, the value should never be less than its
start value and start value does not required to be SCEVConstant.

Reviewed By: nikic, sanjoy

Differential Revision: https://reviews.llvm.org/D71690
2020-01-12 20:22:37 -05:00
James Clarke
9ea03cb0fe [RISCV] Check register class for AMO memory operands
Summary:
AMO memory operands use a custom parser in order to accept both (reg)
and 0(reg). However, the validation predicate used for these operands
was only checking that they were registers, and not the register class,
so non-GPRs (such as FPRs) were also accepted. Thus, fix this by making
the predicate check that they are GPRs.

Reviewers: asb, lenary

Reviewed By: asb, lenary

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72471
2020-01-13 00:50:37 +00:00
Fangrui Song
ab21470fd6 [MC][ELF] Emit a relocation if target is defined in the same section and is non-local
For a target symbol defined in the same section, currently we don't emit
a relocation if VariantKind is VK_None (with few exceptions like RISC-V
relaxation), while GNU as emits one. This causes program behavior
differences with and without -ffunction-sections, and can break intended
symbol interposition in a -shared link.

```
.globl foo
foo:
  call foo      # no relocation. On other targets, may be written as b foo, etc
  call bar      # a relocation if bar is in another section (e.g. -ffunction-sections)
  call foo@plt  # a relocation
```

Unify these cases by always emitting a relocation. If we ever want to
optimize `call foo` in -shared links, we should emit a STB_LOCAL alias
and call via the alias.

ARM/thumb2-beq-fixup.s: we now emit a relocation to global_thumb_fn as GNU as does.
X86/Inputs/align-branch-64-2.s: we now emit R_X86_64_PLT32 to foo as GNU does.

ELF/relax.s: rewrite the test as target-in-same-section.s .
We omitted relocations to `global` and now emit R_X86_64_PLT32.
Note, GNU as does not emit a relocation for `jmp global` (maybe its own
bug). Our new behavior is compatible except `jmp global`.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D72197
2020-01-12 13:46:24 -08:00
Jay Foad
e1678ae631 [AMDGPU] Add gfx8 assembler and disassembler test cases
Summary:
This adds assembler tests for cases that were previously only in the
disassembler tests, and vice versa.

Reviewers: rampitec, arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72561
2020-01-12 21:12:48 +00:00
Fangrui Song
e8e76495e7 __patchable_function_entries: don't use linkage field 'unique' with -no-integrated-as
.section name, "flags"G, @type, GroupName[, linkage]

As of binutils 2.33, linkage cannot be 'unique'.  For integrated
assembler, we use both 'o' flag and 'unique' linkage to support
--gc-sections and COMDAT with lld.

https://sourceware.org/ml/binutils/2019-11/msg00266.html
2020-01-12 12:53:44 -08:00
Markus Böck
0dd9fb199a [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw
Patch by Markus Böck.

Differential Revision: https://reviews.llvm.org/D72564
2020-01-12 14:43:16 -05:00
Fangrui Song
869c74a8ef [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin
Darwin support has been removed.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D72063
2020-01-12 11:02:02 -08:00
Simon Pilgrim
4d186c4684 [MIPS] Regenerate shl/lshr shift tests 2020-01-12 14:35:34 +00:00
Simon Pilgrim
7e136db166 [AMDGPU] Regenerate shl shift tests 2020-01-12 14:34:36 +00:00
Simon Pilgrim
c5b5b336ab [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64 shuffles.
Only perform this if we are shuffling lower and upper lane elements across the lanes (otherwise splitting to lower xmm shuffles would be better).

This is a regression if we shuffle build_vectors due to getVectorShuffle canonicalizing 'blend of splat' build vectors, for now I've set this not to shuffle build_vector nodes at all to avoid this.
2020-01-12 12:29:41 +00:00
Simon Pilgrim
14db9ee673 [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded elements of the lane mask.
Fixes an cyclic dependency issue with an upcoming patch where getVectorShuffle canonicalizes masks with splat build vector sources.
2020-01-12 09:41:40 +00:00
Fangrui Song
f9acff790a [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X86Disassembler.cpp and refactor 2020-01-12 00:53:36 -08:00
Fangrui Song
acc6f07fcd [X86][Disassembler] Simplify 2020-01-12 00:53:35 -08:00