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Author SHA1 Message Date
NAKAMURA Takumi
7a14d1dab9 ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here. 
llvm-svn: 148694
 2012-01-23 09:14:42 +00:00
Chris Lattner
7cf6171afa switch UndefValue and ConstantPointerNull over to DenseMap's for uniquing. 
llvm-svn: 148693
 2012-01-23 08:52:32 +00:00
Nick Lewycky
ccdb5138b7 Fix broken link. 
llvm-svn: 148692
 2012-01-23 08:47:21 +00:00
Chris Lattner
395d1616b3 Replace a use of ConstantUniqueMap for CAZ constants with a simple DenseMap. 
Now that the type system rewrite has landed, there is no need for its
complexity and std::map'ness.

llvm-svn: 148691
 2012-01-23 08:42:38 +00:00
Chris Lattner
0a21f75290 allow OwningPtr to be copy constructed if null, which is required to 
make them be a valuetype in a DenseMap.

llvm-svn: 148688
 2012-01-23 08:19:57 +00:00
Craig Topper
606872615f Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. 
llvm-svn: 148687
 2012-01-23 08:18:28 +00:00
Evgeniy Stepanov
bffa428d01 An option to selectively enable parts of ARM EHABI support. 
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.

llvm-svn: 148686
 2012-01-23 07:57:39 +00:00
Craig Topper
9a78ce373d Update more places to use target specific nodes for vector shifts instead of intrinsics. 
llvm-svn: 148685
 2012-01-23 06:46:22 +00:00
Craig Topper
360c9f28cf Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed. 
llvm-svn: 148684
 2012-01-23 06:16:53 +00:00
Rafael Espindola
02f4d661a1 Avoid using an invalidated iterator. 
llvm-svn: 148681
 2012-01-23 05:07:16 +00:00
Rafael Espindola
c53beeb5f6 The iteration order over a std::set<Module*> depends on the addresses of the 
modules. Avoid that to make the order the linker sees the modules deterministic.

llvm-svn: 148676
 2012-01-23 03:41:53 +00:00
Craig Topper
03b49e88a2 Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments. 
llvm-svn: 148672
 2012-01-23 00:06:44 +00:00
Nick Lewycky
54e62d71e0 Make Value::isDereferenceablePointer() handle unreachable code blocks. (This 
returns false in the event the computation feeding into the pointer is
unreachable, which maybe ought to be true -- but this is at least consistent
with undef->isDereferenceablePointer().) Fixes PR11825!

llvm-svn: 148671
 2012-01-23 00:05:17 +00:00
Craig Topper
b80bb890b6 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. 
llvm-svn: 148670
 2012-01-22 23:36:02 +00:00
Craig Topper
558395cb4e Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching. 
llvm-svn: 148667
 2012-01-22 22:42:16 +00:00
Nicolas Geoffray
dedf43387d Use Attributes::None instead of 0 after r148553 change on Attributes from unsigned to their own class. 
llvm-svn: 148665
 2012-01-22 20:05:26 +00:00
Craig Topper
2b6951f7c4 Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead. 
llvm-svn: 148664
 2012-01-22 19:15:14 +00:00
Anton Korobeynikov
253410c6e6 Add an option to disable buggy copy propagation pass 
llvm-svn: 148662
 2012-01-22 14:08:34 +00:00
NAKAMURA Takumi
999142ef4a unittests/Support/Casting.cpp: [PR8226] Workaround for MSVC|Debug. 
llvm-svn: 148659
 2012-01-22 12:14:35 +00:00
Anton Korobeynikov
76b0745f6c Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!

llvm-svn: 148658
 2012-01-22 12:07:33 +00:00
Eli Bendersky
07d655054e Remove trailing spaces 
llvm-svn: 148655
 2012-01-22 09:26:00 +00:00
Eli Bendersky
2545105c90 Remove trailing spaces 
llvm-svn: 148654
 2012-01-22 09:02:48 +00:00
Eli Bendersky
d2042f3698 Basic runtime dynamic loading capabilities added to ELFObjectFile, implemented 
in a subclass named DyldELFObject. This class supports rebasing the object file
it represents by re-mapping section addresses to the actual memory addresses
the object was placed in. This is required for MC-JIT implementation on ELF with
debugging support.

Patch reviewed on llvm-commits.

Developed together with Ashok Thirumurthi and Andrew Kaylor.

llvm-svn: 148653
 2012-01-22 09:01:03 +00:00
Eli Bendersky
1fa68fd976 Split the lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h header to smaller logical headers. 
ELF and MachO implementations of RuntimeDyldImpl go into their own header files now.

Reviewed on llvm-commits

llvm-svn: 148652
 2012-01-22 07:05:02 +00:00
Craig Topper
5e9b6de71f Make code a little less verbose. 
llvm-svn: 148651
 2012-01-22 03:07:48 +00:00
David Blaikie
05fe2f515d Help GCC along with code that's actually unreachable. 
Unfortunately I don't think there's a fix for this that will work upstream and
also satisfy Clang's -Wunreachable-code, which is a pity. But I'll give it some
more thought -perhaps there's some way out.

llvm-svn: 148645
 2012-01-22 01:17:04 +00:00
Craig Topper
eaca0c20ea Remove unused X86 ISD node type defines. 
llvm-svn: 148644
 2012-01-22 01:15:56 +00:00
Craig Topper
bb07c0da2d Move some vector shift patterns into their instruction definitions. 
llvm-svn: 148643
 2012-01-22 00:41:20 +00:00
Craig Topper
63c59673a3 Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions. 
llvm-svn: 148641
 2012-01-21 18:37:15 +00:00
David Blaikie
93fafabfea Remove unreachable defaults from gtest. 
This will ensure LLVM and Clang build -Wswitch-enum-redundant-default (an on-by-default warning I'm about to add to Clang).

llvm-svn: 148639
 2012-01-21 18:02:01 +00:00
Benjamin Kramer
bdd152e9cf Remove unused variables. 
llvm-svn: 148635
 2012-01-21 10:42:44 +00:00
Craig Topper
d493ca92c4 Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that. 
llvm-svn: 148632
 2012-01-21 08:49:33 +00:00
Evan Cheng
7bd1a126ed Fix an obvious typo. 
llvm-svn: 148622
 2012-01-21 03:31:03 +00:00
Jakob Stoklund Olesen
46feaf86cf Handle register masks in LiveVariables. 
A register mask operand kills any live physreg that isn't preserved.
Unlike an implicit-def operand, the clobbered physregs are never live
afterwards.

This means LiveVariables has to track a much smaller number of live
physregs, and it should spend much less time in addRegisterDead().

llvm-svn: 148609
 2012-01-21 00:58:53 +00:00
Jim Grosbach
e6dc36349b RuntimeDyld alignment adjustment from MachO file. 
The MachO file stores section alignment as log2(alignment-in-bytes). The
allocation routines want the raw alignment-in-bytes value, so adjust
for that.

llvm-svn: 148604
 2012-01-21 00:21:53 +00:00
Jim Grosbach
5100c10a17 Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction. 
llvm-svn: 148601
 2012-01-21 00:07:56 +00:00
Jakob Stoklund Olesen
0eca627fb7 Delete an unused member variable. 
llvm-svn: 148594
 2012-01-20 22:48:59 +00:00
Jim Grosbach
472cca5206 Fix inverted condition. 
llvm-svn: 148593
 2012-01-20 22:44:03 +00:00
Devang Patel
0ecda3fc14 Intel syntax: Robustify register parsing. 
llvm-svn: 148591
 2012-01-20 22:32:05 +00:00
Jakob Stoklund Olesen
85cd4626f4 Support register masks in MachineLICM. 
Only PostRA LICM is affected.

llvm-svn: 148589
 2012-01-20 22:27:12 +00:00
Jakob Stoklund Olesen
704b3cf1d2 Handle register masks in DeadMachineInstructionElim. 
Don't track live physregs that are clobbered by a register mask operand.

llvm-svn: 148588
 2012-01-20 22:27:09 +00:00
David Blaikie
06ecc99a56 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Andrew Trick
207780ec8e Handle a corner case with IV chain collection with bailout instead of assert. 
Fixes PR11783: bad cast to AddRecExpr.

llvm-svn: 148572
 2012-01-20 21:23:40 +00:00
Andrew Trick
343a9ff799 Test case comments missing from my previous checkin. 
llvm-svn: 148571
 2012-01-20 21:21:27 +00:00
Devang Patel
0638a44a24 Intel syntax: Parse ... PTR [-8] 
llvm-svn: 148570
 2012-01-20 21:21:01 +00:00
Devang Patel
e836c95860 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. 
llvm-svn: 148569
 2012-01-20 21:14:06 +00:00
Bob Wilson
793fa215cb ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> 
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
 2012-01-20 20:59:56 +00:00
Jim Grosbach
2b1f17ec6e TblGen diagnostic for mismatched template instantiation. 
Providing a template argment to a non-templatized class was crashing
tblgen. Add a diagnostic.

For example,
$ cat bug.td
class A;

def B : A<0> {
}
$ llvm-tblgen bug.td
bug.td:3:11: error: template argument provided to non-template class
def B : A<0> {
          ^

llvm-svn: 148565
 2012-01-20 20:02:39 +00:00
Jim Grosbach
b6e177bd4e VST2 four-register w/ update pseudos for fixed/register update. 
rdar://10724489

llvm-svn: 148560
 2012-01-20 19:16:00 +00:00
Jim Grosbach
4579f05f36 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00