RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
Code Issues Projects Releases Wiki Activity
79,070 Commits 4 Branches 5 Tags 704 MiB
6839d66ab3
Commit Graph

79070 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Trick
6839d66ab3 Fix SCEVExpander to handle loops with no preheader when LSR gives it a 
"phony" insertion point.

Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert

llvm-svn: 147439
 2012-01-02 21:25:10 +00:00
Duncan Sands
ec8ede7bf4 Correct spelling. 
llvm-svn: 147435
 2012-01-02 16:55:01 +00:00
Chandler Carruth
a2027ac404 Undo the hack in r147427 and move this unittest to a better home. This 
is testing the bitcode reader's functionality, not VMCore's. Add the
what is a hope sufficient build system mojo to build and run a new
unittest.

Also clean up some of the test's naming. The goal for the file should be
to unittest the Bitcode Reader, and this is just one particular test
among potentially many in the future. Also, reverse my position and
relegate the PR# to a comment, but stash the comment on the same line as
the test name so it doesn't get lost. This makes the code more
self-documenting hopefully w/o losing track of the PR number.

llvm-svn: 147431
 2012-01-02 09:19:48 +00:00
Craig Topper
dbc281bcbe Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions. 
llvm-svn: 147430
 2012-01-02 09:17:37 +00:00
Craig Topper
69e0a09d8f Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. 
llvm-svn: 147428
 2012-01-02 08:46:48 +00:00
Chandler Carruth
4ccca7b229 Fix unittest makefile after r147425. This should unbreak the makefile 
build. This didn't show up in the CMake build because the CMake build
for the unittests is rather poorly factored.

This probably isn't the correct fix. This should be a bitcode reader
unittest not a VMCore unittest. I'll move it and clean various parts of
the unittest up in a follow-up patch, but I wanted to unbreak the bots.

llvm-svn: 147427
 2012-01-02 08:40:40 +00:00
Nadav Rotem
6929a8868b Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. 
llvm-svn: 147426
 2012-01-02 08:05:46 +00:00
Rafael Espindola
7ab0861d5f Materialize functions whose basic blocks are used by global variables. Fixes 
PR11677.

llvm-svn: 147425
 2012-01-02 07:49:53 +00:00
Craig Topper
f7c9bf17dd Allow CRC32 instructions to be selected when AVX is enabled. 
llvm-svn: 147411
 2012-01-01 19:51:58 +00:00
Craig Topper
d8ae2d9f27 Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. 
llvm-svn: 147409
 2012-01-01 19:40:22 +00:00
Benjamin Kramer
210900f7c2 X86Disassembler: Fix undefined behavior found by GCC 4.6 
llvm-svn: 147404
 2012-01-01 17:55:36 +00:00
Benjamin Kramer
fba4e88bc2 PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers. 
llvm-svn: 147403
 2012-01-01 17:55:30 +00:00
Benjamin Kramer
450513861d PatternMatch: Simplify code by reusing the Operator class. 
llvm-svn: 147402
 2012-01-01 17:55:23 +00:00
Rafael Espindola
1cb17796db Revert 147399. It broke CodeGen/ARM/vext.ll. 
llvm-svn: 147400
 2012-01-01 17:36:23 +00:00
Elena Demikhovsky
9b74049783 Fixed a bug in SelectionDAG.cpp. 
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.

llvm-svn: 147399
 2012-01-01 16:22:47 +00:00
NAKAMURA Takumi
ad71e57658 Happy new year 2012! 
llvm-svn: 147395
 2012-01-01 08:16:56 +00:00
Craig Topper
ef59fe1ad4 Merge X86 SHUFPS and SHUFPD node types. 
llvm-svn: 147394
 2011-12-31 23:50:21 +00:00
Craig Topper
0311c45aed Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load. 
llvm-svn: 147393
 2011-12-31 23:24:49 +00:00
Craig Topper
c01ce759d7 Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. 
llvm-svn: 147392
 2011-12-31 23:15:11 +00:00
Nick Lewycky
c7e12f7dbf Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate the 
'and' that would zero out the trailing bits, and to produce an exact shift
ourselves.

llvm-svn: 147391
 2011-12-31 21:30:22 +00:00
Dylan Noblesmith
06b6c587e8 VMCore: add assert for miscompile 
See PR11652. Trying to add this assert to
setSubclassData() itself actually prevented
the miscompile entirely, so it has to be here.

This makes the source of the bug more obvious
than the other asserts triggering later on did.

llvm-svn: 147390
 2011-12-31 13:58:58 +00:00
Bruno Cardoso Lopes
4ed60a4736 Cleanup Mips code and rename some variables. Patch by Jack Carter 
llvm-svn: 147383
 2011-12-30 21:09:41 +00:00
Bruno Cardoso Lopes
7de2b7652d Improve Mips JIT. 
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

llvm-svn: 147382
 2011-12-30 21:04:30 +00:00
Nick Lewycky
ed7856bd5b Remove extraneous ".get()->" which is just "->". No functionality change. 
llvm-svn: 147379
 2011-12-30 19:17:23 +00:00
Craig Topper
4065311852 Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. 
llvm-svn: 147369
 2011-12-30 07:16:00 +00:00
Craig Topper
b4db8689ee Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
llvm-svn: 147368
 2011-12-30 06:23:39 +00:00
Craig Topper
089be4fefa Add FMA4 instructions to disassembler. 
llvm-svn: 147367
 2011-12-30 05:20:36 +00:00
Craig Topper
44a5136fac Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
llvm-svn: 147366
 2011-12-30 04:48:54 +00:00
Craig Topper
97ba7b38eb Combine FMA4 SS/SD patterns with the instruction definitions. 
llvm-svn: 147365
 2011-12-30 03:33:59 +00:00
Craig Topper
bdcc86a43c Combine FMA4 PS/PD patterns with the instruction definitions. 
llvm-svn: 147364
 2011-12-30 03:17:15 +00:00
Craig Topper
33091db89a Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. 
llvm-svn: 147361
 2011-12-30 02:18:36 +00:00
Craig Topper
e066262284 Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. 
llvm-svn: 147360
 2011-12-30 01:49:53 +00:00
Hal Finkel
4a09216dfb Cleanup stack/frame register define/kill states. This fixes two bugs: 
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).

2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.

llvm-svn: 147359
 2011-12-30 00:34:00 +00:00
Rafael Espindola
db7319d272 Implement cfi_restore. Patch by Brian Anderson! 
llvm-svn: 147356
 2011-12-29 21:43:03 +00:00
Rafael Espindola
bc8c3d0ca0 Rename Remember and Restore to RememberState and RestoreState for consistency. 
llvm-svn: 147354
 2011-12-29 21:09:08 +00:00
Craig Topper
97e84c23a1 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. 
llvm-svn: 147353
 2011-12-29 20:43:40 +00:00
Rafael Espindola
27298c6f33 Implement .cfi_escape. Patch by Brian Anderson! 
llvm-svn: 147352
 2011-12-29 20:24:47 +00:00
Craig Topper
bcfd070378 Expose FMA3 instructions to the disassembler. 
llvm-svn: 147351
 2011-12-29 20:03:14 +00:00
Craig Topper
9d664349d6 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. 
llvm-svn: 147349
 2011-12-29 19:46:19 +00:00
Craig Topper
21029d1f81 Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit. 
llvm-svn: 147348
 2011-12-29 19:25:56 +00:00
Craig Topper
93d614dd3a Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. 
llvm-svn: 147347
 2011-12-29 18:47:31 +00:00
Craig Topper
ba73cefabb Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. 
llvm-svn: 147345
 2011-12-29 18:08:36 +00:00
Craig Topper
63bb77ebe7 Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. 
llvm-svn: 147344
 2011-12-29 18:00:08 +00:00
Craig Topper
04b3b369de Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. 
llvm-svn: 147342
 2011-12-29 17:41:56 +00:00
Craig Topper
3ff20898e9 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. 
llvm-svn: 147339
 2011-12-29 15:51:45 +00:00
Craig Topper
0ff84d82cc Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8. 
llvm-svn: 147337
 2011-12-29 03:34:54 +00:00
Craig Topper
cb884f28d9 Remove some elses after returns. 
llvm-svn: 147336
 2011-12-29 03:20:51 +00:00
Craig Topper
4cbe88ceba Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path. 
llvm-svn: 147335
 2011-12-29 03:09:33 +00:00
Rafael Espindola
1935193ab7 Fix grammar error noticed by Duncan. 
llvm-svn: 147333
 2011-12-29 02:15:06 +00:00
Nick Lewycky
7425820374 Change CaptureTracking to pass a Use* instead of a Value* when a value is 
captured. This allows the tracker to look at the specific use, which may be
especially interesting for function calls.

Use this to fix 'nocapture' deduction in FunctionAttrs. The existing one does
not iterate until a fixpoint and does not guarantee that it produces the same
result regardless of iteration order. The new implementation builds up a graph
of how arguments are passed from function to function, and uses a bottom-up walk
on the argument-SCCs to assign nocapture. This gets us nocapture more often, and
does so rather efficiently and independent of iteration order.

llvm-svn: 147327
 2011-12-28 23:24:21 +00:00