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293 Commits

Author SHA1 Message Date
Jim Grosbach
0ae6bf8095 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
Owen Anderson
bba3b2050e Add tests for NEON encoding of vmull. 
llvm-svn: 117077
 2010-10-21 22:19:53 +00:00
Jim Grosbach
7c42142b71 ARM binary encodings for MVN variants. 
llvm-svn: 117076
 2010-10-21 22:19:32 +00:00
Owen Anderson
653fc9304a Add tests for NEON encoding of vqdmulh and vqrdmulh. 
llvm-svn: 117074
 2010-10-21 22:05:33 +00:00
Jim Grosbach
cb41e97b5c ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Owen Anderson
2c25ce7af1 Add tests for NEON vmul encoding. 
llvm-svn: 117069
 2010-10-21 21:51:58 +00:00
Owen Anderson
b0bddd3282 Rename this test to better reflect its contents. 
llvm-svn: 117067
 2010-10-21 21:40:15 +00:00
Owen Anderson
77c5078d4a Add tests for NEON encodings of vaddhn and vraddhn. 
llvm-svn: 117064
 2010-10-21 20:56:57 +00:00
Owen Anderson
ba6ee305cf Add tests for NEON encodings of vqadd, which was already correctly encoded. 
llvm-svn: 117059
 2010-10-21 20:42:04 +00:00
Owen Anderson
51a6bc3b27 Add correct NEON encodings for vhadd and vrhadd. 
llvm-svn: 117047
 2010-10-21 18:55:04 +00:00
Owen Anderson
dce283c7db Add correct encodings for NEON vaddw.s* and vaddw.u*. 
llvm-svn: 117040
 2010-10-21 18:20:25 +00:00
Owen Anderson
7d90c72edf Provide correct NEON encodings for vaddl.u* and vaddl.s*. 
llvm-svn: 117039
 2010-10-21 18:09:17 +00:00
Bill Wendling
8b2c8a5856 Fix whitespace. 
llvm-svn: 117002
 2010-10-21 06:25:08 +00:00
Andrew Trick
4a3b819c1f putback r116983 and fix simple-fp-encoding.ll tests 
llvm-svn: 116992
 2010-10-21 03:40:16 +00:00
Owen Anderson
a685f8e90a Implement correct encodings for NEON vadd, both integer and floating point. 
llvm-svn: 116981
 2010-10-21 00:48:00 +00:00
Bill Wendling
c7ef66fcf2 Add encoding for moving a value between two ARM core registers and a doublework 
extension register.

llvm-svn: 116970
 2010-10-20 23:37:40 +00:00
Bill Wendling
0f96ff63b3 Add encodings for movement between ARM core registers and single-precision 
registers.

llvm-svn: 116961
 2010-10-20 22:44:54 +00:00
Jim Grosbach
67f94c42d8 ARM mode encoding information for UBFX and SBFX instructions. 
llvm-svn: 116588
 2010-10-15 17:15:16 +00:00
Jim Grosbach
608e4fd221 Simplify test file a bit. 
llvm-svn: 116540
 2010-10-14 23:32:44 +00:00
Jim Grosbach
26842cb893 Add testcase for RRX and ASRS (which effectively tests MOVs, since those 
are just forms of that instruction).

llvm-svn: 116538
 2010-10-14 23:29:18 +00:00
Jim Grosbach
73c78f8790 MOVi16 and MOVT ARM mode encodings. 
llvm-svn: 116498
 2010-10-14 18:54:27 +00:00
Bill Wendling
2c335d364c Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on 
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

llvm-svn: 116471
 2010-10-14 02:33:26 +00:00
Bill Wendling
33a2ecd5e4 Add encoding for 'fmstat'. 
llvm-svn: 116466
 2010-10-14 01:19:34 +00:00
Bill Wendling
cd41f22ec1 - Add encodings for multiply add/subtract instructions in all their glory. 
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464
 2010-10-14 01:02:08 +00:00
Bill Wendling
bf63d6eb63 Add MC encodings for VCVT* instrunctions. 
llvm-svn: 116431
 2010-10-13 20:58:46 +00:00
Jim Grosbach
8f0bea85bf Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach
9c4a598ef2 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
llvm-svn: 116412
 2010-10-13 18:00:52 +00:00
Bill Wendling
6d8a23c978 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test 
just yet.

llvm-svn: 116386
 2010-10-13 01:17:33 +00:00
Bill Wendling
ea062d454d Add encodings for VCVT instructions. 
llvm-svn: 116385
 2010-10-13 00:56:35 +00:00
Jim Grosbach
3fe0337063 Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

llvm-svn: 116384
 2010-10-13 00:50:27 +00:00
Bill Wendling
e6c2fdebbd Add VCMPZ and VABS. 
llvm-svn: 116383
 2010-10-13 00:38:07 +00:00
Bill Wendling
fddde4cc72 Refactor VCMP instructions. 
llvm-svn: 116379
 2010-10-13 00:04:29 +00:00
Bill Wendling
47155cfddd Add encodings for VNMUL[SD]. 
llvm-svn: 116375
 2010-10-12 23:47:37 +00:00
Bill Wendling
185b548b07 Add encodings for VDIV and VMUL. 
llvm-svn: 116370
 2010-10-12 23:22:27 +00:00
Jim Grosbach
0038f2eec6 Be nitpicky and line up the comments. 
llvm-svn: 116365
 2010-10-12 23:14:03 +00:00
Bill Wendling
cd3cb8da45 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359
 2010-10-12 22:55:35 +00:00
Bill Wendling
fad2800dbd Don't need to specify calling convention. Add 'readnone' to functions. 
llvm-svn: 116354
 2010-10-12 22:24:10 +00:00
Bill Wendling
33a26354c1 Encoding for VADDD. Plus a test for the VFP instructions. 
llvm-svn: 116348
 2010-10-12 22:08:41 +00:00
Jim Grosbach
10d9bbe0ca Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

llvm-svn: 116313
 2010-10-12 17:11:26 +00:00
Jim Grosbach
29ef87e765 MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

llvm-svn: 116259
 2010-10-11 23:16:21 +00:00
Jim Grosbach
3075d28c15 Implement a few more binary encoding bits. Still very early stage proof-of- 
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112
 2010-10-08 21:45:55 +00:00
Jim Grosbach
edbbf33203 Add test file for simple ARM binary encodings with MC 
llvm-svn: 116024
 2010-10-08 00:47:59 +00:00
Chris Lattner
3528fce592 move ARM MC tests up one level. 
llvm-svn: 115414
 2010-10-02 18:52:05 +00:00