RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
Code Issues Projects Releases Wiki Activity
60,842 Commits 4 Branches 5 Tags 704 MiB
696fbed514
Commit Graph

60842 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jakob Stoklund Olesen
696fbed514 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627
 2010-05-25 19:49:33 +00:00
Daniel Dunbar
15b9844a05 MC/X86: Add a hack to allow recognizing 'cmpltps' and friends. 
llvm-svn: 104626
 2010-05-25 19:49:32 +00:00
Dale Johannesen
8fd73c1910 Fix another variant of PR 7191. Also add a testcase 
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624
 2010-05-25 18:47:23 +00:00
Daniel Dunbar
28018eed17 MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. 
llvm-svn: 104622
 2010-05-25 18:40:53 +00:00
Kevin Enderby
e336aaa32b The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required 
for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621
 2010-05-25 18:16:58 +00:00
Dale Johannesen
42c91e9024 Fix PR 7191. I have been unable to create a .ll file that fails, sorry. 
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)

llvm-svn: 104619
 2010-05-25 17:50:03 +00:00
Eric Christopher
627e887b3d Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638

llvm-svn: 104617
 2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen
6e7961be11 Ignore NumberHack and give each SubRegIndex instance a unique enum value instead. 
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

llvm-svn: 104615
 2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
56e4442b2c Use enums instead of literals for SystemZ subregisters 
llvm-svn: 104612
 2010-05-25 17:04:18 +00:00
Jakob Stoklund Olesen
201408751f Use enums instead of literals for X86 subregisters. 
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.

llvm-svn: 104611
 2010-05-25 17:04:16 +00:00
Zonr Chang
465ebb1bcf Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate)) 
llvm-svn: 104588
 2010-05-25 10:23:52 +00:00
Zonr Chang
5ce8b82ebf Add support to MOVimm32 using movt/movw for ARM JIT 
llvm-svn: 104587
 2010-05-25 08:42:45 +00:00
Bob Wilson
bcd0854609 Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated. 
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.

llvm-svn: 104583
 2010-05-25 04:51:47 +00:00
Bob Wilson
c8bea44d68 Fix up instruction classes for Thumb2 RSB instructions to be consistent with 
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.

llvm-svn: 104582
 2010-05-25 04:43:08 +00:00
Bob Wilson
49df2d928d Clean up indentation. 
llvm-svn: 104580
 2010-05-25 03:36:52 +00:00
Jakob Stoklund Olesen
3e9a143416 Disable invalid coalescer assertion. 
llvm-svn: 104574
 2010-05-25 00:15:18 +00:00
Jakob Stoklund Olesen
3f68e903d7 Use enums instead of literals in the ARM backend. 
llvm-svn: 104573
 2010-05-25 00:15:15 +00:00
Bill Wendling
ba69a15fc0 Print out the name of the function during SSC. 
llvm-svn: 104572
 2010-05-24 23:16:04 +00:00
Jakob Stoklund Olesen
d1f4d14609 Switch SubRegSet to using symbolic SubRegIndices 
llvm-svn: 104571
 2010-05-24 23:03:18 +00:00
Bob Wilson
b5c1a4be63 Allow Thumb2 MVN instructions to set condition codes. The immediate operand 
version of t2MVN already allowed that, but not the register versions.

llvm-svn: 104570
 2010-05-24 22:41:19 +00:00
Chris Lattner
6ea2f4d4cc diaggroup categories should take precedence over diag-specific groups. 
llvm-svn: 104567
 2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
e3f6ea45b2 Lose the dummies 
llvm-svn: 104564
 2010-05-24 21:47:01 +00:00
Jakob Stoklund Olesen
3a19b732d8 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
 2010-05-24 21:46:58 +00:00
Evan Cheng
e34814c0bc Avoid adding duplicate function live-in's. 
llvm-svn: 104560
 2010-05-24 21:33:37 +00:00
Dan Gohman
824858ebb0 Fix an mmx movd encoding. 
llvm-svn: 104552
 2010-05-24 20:51:08 +00:00
Kevin Enderby
a911679139 MC/X86: Add aliases for CMOVcc variants. 
llvm-svn: 104549
 2010-05-24 20:32:23 +00:00
Bob Wilson
e6a30dc530 Clean up some extra whitespace. 
llvm-svn: 104544
 2010-05-24 20:08:34 +00:00
Bob Wilson
c71b7c8c61 Thumb2 RSBS instructions were being printed without the 'S' suffix. 
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.

llvm-svn: 104531
 2010-05-24 18:44:06 +00:00
Devang Patel
345bc8667e Do not emit line number entries for unknown debug values. 
This fixes recent regression in store.exp from gdb testsuite.

llvm-svn: 104524
 2010-05-24 18:26:49 +00:00
Evan Cheng
9b011e343c LR is in GPR, not tGPR even in Thumb1 mode. 
llvm-svn: 104518
 2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
4f2bfd8451 Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are 
never used.

llvm-svn: 104517
 2010-05-24 17:55:38 +00:00
Jakob Stoklund Olesen
26bb6fd4f2 Use SubRegIndex in SystemZ. 
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.

llvm-svn: 104515
 2010-05-24 17:43:01 +00:00
Jakob Stoklund Olesen
7c5127a0c6 SubRegIndex'ize Mips 
llvm-svn: 104514
 2010-05-24 17:42:58 +00:00
Jakob Stoklund Olesen
6d971535b8 SubRegIndex'ize MSP430 
llvm-svn: 104513
 2010-05-24 17:42:55 +00:00
Jakob Stoklund Olesen
d48a2f5afd Fix a few places that depended on the numeric value of subreg indices. 
Add assertions in places that depend on consecutive indices.

llvm-svn: 104510
 2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
ac6f519e79 Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums 
from ARMRegisterInfo.h

llvm-svn: 104508
 2010-05-24 16:54:32 +00:00
Jakob Stoklund Olesen
f40bb16b94 Rename X86 subregister indices to something shorter. 
Use the tablegen-produced enums.

llvm-svn: 104493
 2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
9a54fec092 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
 2010-05-24 14:48:12 +00:00
Nicolas Geoffray
803f2761ec Encode the Caml frametable by following what the comment says: the number of descriptors 
is first emitted, and StackOffsets are emitted in 16 bits.

llvm-svn: 104488
 2010-05-24 12:24:11 +00:00
Duncan Sands
f2bec8edf6 Apply timeouts and memory limits in more places. In particular, when 
bugpoint does "Running the code generator to test for a crash" this
gets you a crash if llc goes into an infinite loop or uses up vast
amounts of memory.

llvm-svn: 104485
 2010-05-24 07:49:55 +00:00
Daniel Dunbar
5bef2f5031 llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better. 
llvm-svn: 104467
 2010-05-23 18:36:38 +00:00
Daniel Dunbar
e87e067d2c llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better. 
llvm-svn: 104466
 2010-05-23 18:36:34 +00:00
Daniel Dunbar
eb23d9ac22 MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches. 
llvm-svn: 104463
 2010-05-23 17:44:06 +00:00
Bob Wilson
c7efe760d6 VDUP doesn't support vectors with 64-bit elements. 
llvm-svn: 104455
 2010-05-23 05:42:31 +00:00
Daniel Dunbar
50265dbaf0 MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: 
addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

llvm-svn: 104453
 2010-05-22 21:02:33 +00:00
Daniel Dunbar
ee525943d8 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
llvm-svn: 104452
 2010-05-22 21:02:29 +00:00
Daniel Dunbar
7c60f7caa2 MC/X86: Add alias for setz, setnz, jz, jnz. 
llvm-svn: 104435
 2010-05-22 06:37:33 +00:00
John Mosby
cec9b7fc9c Trivial change to dump() function for SparseBitVector 
llvm-svn: 104433
 2010-05-22 05:13:17 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977. 
llvm-svn: 104421
 2010-05-22 01:47:14 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00