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18646 Commits

Author SHA1 Message Date
Owen Anderson
2e722e7cd4 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. 
llvm-svn: 137686
 2011-08-15 23:38:54 +00:00
Bruno Cardoso Lopes
f026c60f3d While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG and 
also add the AVX versions of the 128-bit patterns

llvm-svn: 137685
 2011-08-15 23:36:51 +00:00
Bruno Cardoso Lopes
1e817d1451 Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

llvm-svn: 137684
 2011-08-15 23:36:45 +00:00
Jim Grosbach
31c0c9a1f6 MCTargetAsmParser target match predicate support. 
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675
 2011-08-15 23:03:29 +00:00
Bruno Cardoso Lopes
b81c3ed76d Fix PR10656. It's only profitable to use 128-bit inserts and extracts 
when AVX mode is one. Otherwise is just more work for the type
legalizer.

llvm-svn: 137661
 2011-08-15 21:45:54 +00:00
Owen Anderson
42946000dd Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Owen Anderson
f86afc2459 Remove dead classes. 
llvm-svn: 137643
 2011-08-15 20:11:11 +00:00
Owen Anderson
4854258d9c Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
llvm-svn: 137641
 2011-08-15 20:08:25 +00:00
Owen Anderson
cd94fca93d Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
llvm-svn: 137636
 2011-08-15 19:00:06 +00:00
Owen Anderson
894585de33 Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Jim Grosbach
b2b673661a Update comment to reflect MC target machine refactor. 
llvm-svn: 137615
 2011-08-15 16:52:24 +00:00
Bob Wilson
90799621b3 Expand VMOVQQQQ pseudo instructions. 
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551
 2011-08-13 05:14:55 +00:00
Jim Grosbach
4b198ae6d5 ARM STR_POST_IMM offset encoding fix in load/store optimizer. 
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.

rdar://9945172

llvm-svn: 137525
 2011-08-12 22:20:41 +00:00
Bruno Cardoso Lopes
8bdbc680ea Fix comment! 
llvm-svn: 137521
 2011-08-12 21:54:42 +00:00
Bruno Cardoso Lopes
2d100ca13c The VPERM2F128 is a AVX instruction which permutes between two 256-bit 
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

llvm-svn: 137519
 2011-08-12 21:48:26 +00:00
Bruno Cardoso Lopes
17ae896095 Move code around and add comments 
llvm-svn: 137518
 2011-08-12 21:48:22 +00:00
Akira Hatanaka
c9c0190cbe Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Jim Grosbach
2e48dbda92 ARM expansion of pre-indexed store pseudos should maintain memoperands. 
Partial fix for rdar://9945172.

llvm-svn: 137513
 2011-08-12 21:02:34 +00:00
Owen Anderson
2ea55a0881 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson
7b426d97ad Fix decoding of ARM-mode STRH. 
llvm-svn: 137499
 2011-08-12 20:02:50 +00:00
Owen Anderson
9162ba81cf Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings. 
llvm-svn: 137494
 2011-08-12 19:41:29 +00:00
Owen Anderson
322b9ce8bf Fix decoding of pre-indexed stores. 
llvm-svn: 137487
 2011-08-12 18:12:39 +00:00
Akira Hatanaka
5706262bc2 When constant double 0.0 is lowered, make sure 0 is copied directly from an 
integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.

- In the test case, the following code is generated before this patch is
  applied:
mtc1  $zero, $f2    ; unformatted copy to $f2
mov.s $f0, $f2      ; $f0 is in single format
sdc1  $f12, 0($sp)
mov.s $f1, $f2      ; $f1 is in single format
c.eq.d  $f12, $f0   ; $f0 cannot be interpreted as double

- The following code is generated after this patch is applied:
mtc1  $zero, $f0    ; unformatted copy to $f0
mtc1  $zero, $f1    ; unformatted copy to $f1
c.eq.d  $f12, $f0   ; $f0 can be interpreted as double

Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.

llvm-svn: 137484
 2011-08-12 18:09:59 +00:00
Chris Lattner
109982ca44 switch to the new struct apis. 
llvm-svn: 137481
 2011-08-12 18:07:07 +00:00
Owen Anderson
a1df383bae Separate decoding for STREXD and LDREXD to make each work better. 
llvm-svn: 137476
 2011-08-12 17:58:32 +00:00
Duncan Sands
10a9e984bc Silence a bunch (but not all) "variable written but not read" warnings 
when building with assertions disabled.

llvm-svn: 137460
 2011-08-12 14:54:45 +00:00
Andrew Trick
68f830e252 findDeadCallerSavedReg fix: Missing NULL terminator in register arrays. 
Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.

llvm-svn: 137404
 2011-08-12 00:49:19 +00:00
Jim Grosbach
d17df06881 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Akira Hatanaka
b787f8a8a5 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 

llvm-svn: 137378
 2011-08-11 22:42:31 +00:00
Jim Grosbach
c0560c4013 Remove no-longer-true comments. These are for the assembler, also. 
llvm-svn: 137375
 2011-08-11 22:30:30 +00:00
Jim Grosbach
edefbb31c3 ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Owen Anderson
634422d756 Make the USAT16 operand decoder auto-generate-able. 
llvm-svn: 137371
 2011-08-11 22:10:11 +00:00
Owen Anderson
8a55a4d7be Add another accidentally omitted predicate operand. 
llvm-svn: 137370
 2011-08-11 22:08:38 +00:00
Owen Anderson
253a691ae5 Add missing predicate operand on SMLA and friends. 
llvm-svn: 137368
 2011-08-11 22:05:38 +00:00
Jim Grosbach
ed8a320007 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Owen Anderson
42056f92f5 Handle new register classes in Thumb2 mode. Should fix the ARM buildbots. 
llvm-svn: 137364
 2011-08-11 21:52:38 +00:00
Owen Anderson
3e98fed9bc Making SEL decodings auto-generate-able. 
llvm-svn: 137363
 2011-08-11 21:50:56 +00:00
Bruno Cardoso Lopes
328a6a980b Add a dag combine to xform 256-bit shuffles into simple vector 
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

llvm-svn: 137362
 2011-08-11 21:50:44 +00:00
Jim Grosbach
0eb731957b Tidy up comment. 
llvm-svn: 137359
 2011-08-11 21:41:59 +00:00
Owen Anderson
64c500c7dd Fix decoding support for STREXD and LDREXD. 
llvm-svn: 137356
 2011-08-11 21:34:58 +00:00
Jim Grosbach
5c12d41c95 ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Akira Hatanaka
e8e203f116 Add isIndirectBranch flag. 
llvm-svn: 137351
 2011-08-11 21:05:37 +00:00
Owen Anderson
4618d77bcd Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Jim Grosbach
15351f4f22 Tidy up. Remove unused template parameter. 
llvm-svn: 137345
 2011-08-11 20:41:13 +00:00
Owen Anderson
1ec4fcb5d3 Improve operand validation for Thumb2 addressing modes. 
llvm-svn: 137344
 2011-08-11 20:40:40 +00:00
Jim Grosbach
81b2835f83 ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Owen Anderson
73e7d34732 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach
92a220276d Tidy up. 
llvm-svn: 137339
 2011-08-11 20:13:35 +00:00
Jim Grosbach
bfc85134c2 ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach
e6bd3a1ab8 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00