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Author SHA1 Message Date
Jim Grosbach
4b198ae6d5 ARM STR_POST_IMM offset encoding fix in load/store optimizer. 
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.

rdar://9945172

llvm-svn: 137525
 2011-08-12 22:20:41 +00:00
Bruno Cardoso Lopes
8bdbc680ea Fix comment! 
llvm-svn: 137521
 2011-08-12 21:54:42 +00:00
Bruno Cardoso Lopes
2d100ca13c The VPERM2F128 is a AVX instruction which permutes between two 256-bit 
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

llvm-svn: 137519
 2011-08-12 21:48:26 +00:00
Bruno Cardoso Lopes
17ae896095 Move code around and add comments 
llvm-svn: 137518
 2011-08-12 21:48:22 +00:00
Akira Hatanaka
c9c0190cbe Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Jim Grosbach
2e48dbda92 ARM expansion of pre-indexed store pseudos should maintain memoperands. 
Partial fix for rdar://9945172.

llvm-svn: 137513
 2011-08-12 21:02:34 +00:00
Bill Wendling
f57d39d13d Add checks for the landingpad instruction's clause values to make sure that 
they're the correct type.

llvm-svn: 137511
 2011-08-12 20:52:25 +00:00
Owen Anderson
2ea55a0881 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Bill Wendling
4cbbcd4f82 Initial commit of the 'landingpad' instruction. 
This implements the 'landingpad' instruction. It's used to indicate that a basic
block is a landing pad. There are several restrictions on its use (see
LangRef.html for more detail). These restrictions allow the exception handling
code to gather the information it needs in a much more sane way.

This patch has the definition, implementation, C interface, parsing, and bitcode
support in it.

llvm-svn: 137501
 2011-08-12 20:24:12 +00:00
Owen Anderson
7b426d97ad Fix decoding of ARM-mode STRH. 
llvm-svn: 137499
 2011-08-12 20:02:50 +00:00
Owen Anderson
9162ba81cf Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings. 
llvm-svn: 137494
 2011-08-12 19:41:29 +00:00
Owen Anderson
322b9ce8bf Fix decoding of pre-indexed stores. 
llvm-svn: 137487
 2011-08-12 18:12:39 +00:00
Devang Patel
5901733259 Use ArrayRef. 
llvm-svn: 137485
 2011-08-12 18:10:19 +00:00
Akira Hatanaka
5706262bc2 When constant double 0.0 is lowered, make sure 0 is copied directly from an 
integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.

- In the test case, the following code is generated before this patch is
  applied:
mtc1  $zero, $f2    ; unformatted copy to $f2
mov.s $f0, $f2      ; $f0 is in single format
sdc1  $f12, 0($sp)
mov.s $f1, $f2      ; $f1 is in single format
c.eq.d  $f12, $f0   ; $f0 cannot be interpreted as double

- The following code is generated after this patch is applied:
mtc1  $zero, $f0    ; unformatted copy to $f0
mtc1  $zero, $f1    ; unformatted copy to $f1
c.eq.d  $f12, $f0   ; $f0 can be interpreted as double

Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.

llvm-svn: 137484
 2011-08-12 18:09:59 +00:00
Chris Lattner
d297c1dd99 add ifdef's to let people easily remove these dead api for testing. 
llvm-svn: 137483
 2011-08-12 18:08:19 +00:00
Chris Lattner
92ac219e38 switch to the new struct api. 
llvm-svn: 137482
 2011-08-12 18:07:26 +00:00
Chris Lattner
109982ca44 switch to the new struct apis. 
llvm-svn: 137481
 2011-08-12 18:07:07 +00:00
Chris Lattner
ef56f8992d switch to use the new api for structtypes. 
llvm-svn: 137480
 2011-08-12 18:06:37 +00:00
Chris Lattner
605a2173f8 forward to the correct constructor. 
llvm-svn: 137479
 2011-08-12 18:03:30 +00:00
Devang Patel
f54def9bad Provide fast path as Jakob suggested. 
llvm-svn: 137478
 2011-08-12 18:01:34 +00:00
Owen Anderson
a1df383bae Separate decoding for STREXD and LDREXD to make each work better. 
llvm-svn: 137476
 2011-08-12 17:58:32 +00:00
Chris Lattner
7f69a7da6e add two missing function impls 
llvm-svn: 137470
 2011-08-12 17:43:05 +00:00
Chris Lattner
d666fbc755 add new accessors to reflect new terminology in struct types. 
llvm-svn: 137468
 2011-08-12 17:31:02 +00:00
Nadav Rotem
5703db96f2 Revert r137310 because it does not optimize any code on ToT 
llvm-svn: 137466
 2011-08-12 17:15:04 +00:00
Chad Rosier
dcc47fe41a Whitespace and formatting. No functional change intended. 
llvm-svn: 137463
 2011-08-12 16:45:18 +00:00
Duncan Sands
10a9e984bc Silence a bunch (but not all) "variable written but not read" warnings 
when building with assertions disabled.

llvm-svn: 137460
 2011-08-12 14:54:45 +00:00
Benjamin Kramer
e404b3e2d1 MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does. 
llvm-svn: 137414
 2011-08-12 01:51:29 +00:00
Andrew Trick
68f830e252 findDeadCallerSavedReg fix: Missing NULL terminator in register arrays. 
Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.

llvm-svn: 137404
 2011-08-12 00:49:19 +00:00
Dan Gohman
c188a47b62 Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result 
is returned through a bitcast.

llvm-svn: 137402
 2011-08-12 00:36:31 +00:00
Dan Gohman
783fdc6375 Don't let arbitrary calls disrupt nested retain+release pairs if 
the retains and releases all use the same SSA pointer value.

Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.

llvm-svn: 137399
 2011-08-12 00:26:31 +00:00
Dan Gohman
0b4ede167a Use an actual reverse-CFG reverse-postorder for the bottom-up traversal, 
rather than plain postorder, so that CFG constructs like single-exit loops
are reliably visited in a sensible order.

llvm-svn: 137398
 2011-08-12 00:24:29 +00:00
Jakob Stoklund Olesen
024df8fa6b Simplify the interference checking code a bit. 
This is possible now that we now longer provide an interface to iterate
the interference overlaps.

llvm-svn: 137397
 2011-08-12 00:22:04 +00:00
Jim Grosbach
d17df06881 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Andrew Trick
5a5a5ebe68 Allow loop unrolling to get known trip counts from ScalarEvolution. 
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.

This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.

llvm-svn: 137384
 2011-08-11 23:36:16 +00:00
Jakob Stoklund Olesen
911b7966fe Remove the InterferenceResult class. 
llvm-svn: 137381
 2011-08-11 22:46:06 +00:00
Jakob Stoklund Olesen
159343e267 Eliminate the last use of InterferenceResult. 
The Query class now holds two iterators instead of an InterferenceResult
instance. The iterators are used as bookmarks for repeated
collectInterferingVRegs calls.

llvm-svn: 137380
 2011-08-11 22:46:04 +00:00
Akira Hatanaka
b787f8a8a5 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 

llvm-svn: 137378
 2011-08-11 22:42:31 +00:00
Jim Grosbach
c0560c4013 Remove no-longer-true comments. These are for the assembler, also. 
llvm-svn: 137375
 2011-08-11 22:30:30 +00:00
Jim Grosbach
edefbb31c3 ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Owen Anderson
634422d756 Make the USAT16 operand decoder auto-generate-able. 
llvm-svn: 137371
 2011-08-11 22:10:11 +00:00
Owen Anderson
8a55a4d7be Add another accidentally omitted predicate operand. 
llvm-svn: 137370
 2011-08-11 22:08:38 +00:00
Owen Anderson
253a691ae5 Add missing predicate operand on SMLA and friends. 
llvm-svn: 137368
 2011-08-11 22:05:38 +00:00
Jim Grosbach
ed8a320007 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Owen Anderson
42056f92f5 Handle new register classes in Thumb2 mode. Should fix the ARM buildbots. 
llvm-svn: 137364
 2011-08-11 21:52:38 +00:00
Owen Anderson
3e98fed9bc Making SEL decodings auto-generate-able. 
llvm-svn: 137363
 2011-08-11 21:50:56 +00:00
Bruno Cardoso Lopes
328a6a980b Add a dag combine to xform 256-bit shuffles into simple vector 
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

llvm-svn: 137362
 2011-08-11 21:50:44 +00:00
Jim Grosbach
0eb731957b Tidy up comment. 
llvm-svn: 137359
 2011-08-11 21:41:59 +00:00
Owen Anderson
64c500c7dd Fix decoding support for STREXD and LDREXD. 
llvm-svn: 137356
 2011-08-11 21:34:58 +00:00
Jakob Stoklund Olesen
be84676224 Remove more dead code. 
collectInterferingVRegs will be the primary function for interference
checks.

llvm-svn: 137354
 2011-08-11 21:18:34 +00:00
Jim Grosbach
5c12d41c95 ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Dan Gohman
93efd104ca Fix typos in comments, and delete an unused function. 
llvm-svn: 137352
 2011-08-11 21:06:32 +00:00
Akira Hatanaka
e8e203f116 Add isIndirectBranch flag. 
llvm-svn: 137351
 2011-08-11 21:05:37 +00:00
Jakob Stoklund Olesen
c5ce5edb07 Privatize an unused part of the LiveIntervalUnion::Query interface. 
No clients are iterating over interference overlaps.

llvm-svn: 137350
 2011-08-11 21:00:42 +00:00
Owen Anderson
4618d77bcd Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Jakob Stoklund Olesen
2fd36775a3 Remove some dead code. 
The InterferenceResult iterator turned out to be less important than we
thought it would be.  LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.

llvm-svn: 137346
 2011-08-11 20:41:41 +00:00
Jim Grosbach
15351f4f22 Tidy up. Remove unused template parameter. 
llvm-svn: 137345
 2011-08-11 20:41:13 +00:00
Owen Anderson
1ec4fcb5d3 Improve operand validation for Thumb2 addressing modes. 
llvm-svn: 137344
 2011-08-11 20:40:40 +00:00
Jim Grosbach
81b2835f83 ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Andrew Trick
b31724d9ff Fix for LoopInfo::updateUnloop. Remove subloop blocks from former 
ancestor loops.

I have a unit test that depends on scev-unroll, which unfortunately
isn't checked in. But I will check it in when I can.

llvm-svn: 137341
 2011-08-11 20:27:32 +00:00
Owen Anderson
73e7d34732 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach
92a220276d Tidy up. 
llvm-svn: 137339
 2011-08-11 20:13:35 +00:00
Jim Grosbach
bfc85134c2 ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach
e6bd3a1ab8 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Owen Anderson
63ccfdccd1 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes
38d4afa02f Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. 
llvm-svn: 137324
 2011-08-11 18:59:13 +00:00
Owen Anderson
decc5fcced Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson
707fcaca0e Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
llvm-svn: 137322
 2011-08-11 18:41:59 +00:00
Benjamin Kramer
de2c60be28 Plug a memory leak. 
llvm-svn: 137321
 2011-08-11 18:39:28 +00:00
Owen Anderson
8d6b9f063f Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00
Jim Grosbach
9717a9c0d3 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Andrew Trick
eb6a7aad9e Cleanup. Another thorough review by Nick! 
llvm-svn: 137317
 2011-08-11 17:54:58 +00:00
Jim Grosbach
abaaf4513f ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Nadav Rotem
2461d23062 Add a comment, per Bruno's CR. 
llvm-svn: 137313
 2011-08-11 17:05:47 +00:00
Nadav Rotem
b738be4555 [AVX] When joining two XMM registers into a YMM register, make sure that the 
lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 

llvm-svn: 137310
 2011-08-11 16:49:36 +00:00
Nadav Rotem
de1b485f3f [AVX] If the data which is going to be saved is already in two XMM registers 
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)

llvm-svn: 137308
 2011-08-11 16:41:21 +00:00
Chris Lattner
575057916a fix PR10605 / rdar://9930964 by adding a pretty scary missed check. 
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303
 2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes
4106caa9af Cleanup: Remove Int_ CVTSS2SI* forms 
llvm-svn: 137297
 2011-08-11 02:52:36 +00:00
Bruno Cardoso Lopes
8674ddf55a Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing 
infinite recursive calls in legalize. Fix PR10562

llvm-svn: 137296
 2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes
954ac403c7 Use the splat index to generate the desired shuffle. Otherwise we 
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

llvm-svn: 137295
 2011-08-11 02:49:41 +00:00
Eli Friedman
17bd9e5d7c Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). 
Fixes PR9693.

llvm-svn: 137292
 2011-08-11 01:48:05 +00:00
Devang Patel
504551c7bf Stay within 80 columns. 
llvm-svn: 137283
 2011-08-10 23:58:09 +00:00
Jim Grosbach
5322f1ea74 ARM LDRT assembly parsing and encoding. 
llvm-svn: 137282
 2011-08-10 23:43:54 +00:00
Jim Grosbach
9fd458fd63 Tidy up. 80 columns. 
llvm-svn: 137277
 2011-08-10 23:23:47 +00:00
Andrew Trick
306e3d0508 Reapplying r136844. 
An algorithm for incrementally updating LoopInfo within a
LoopPassManager. The incremental update should be extremely cheap in
most cases and can be used in places where it's not feasible to
regenerate the entire loop forest.

- "Unloop" is a node in the loop tree whose last backedge has been removed.
- Perform reverse dataflow on the block inside Unloop to propagate the
  nearest loop from the block's successors.
- For reducible CFG, each block in unloop is visited exactly
  once. This is because unloop no longer has a backedge and blocks
  within subloops don't change parents.
- Immediate subloops are summarized by the nearest loop reachable from
  their exits or exits within nested subloops.
- At completion the unloop blocks each have a new parent loop, and
  each immediate subloop has a new parent.

llvm-svn: 137276
 2011-08-10 23:22:57 +00:00
Jim Grosbach
e0ccd6b34e ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach
4ad2dc8bb2 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Devang Patel
1541972a13 Distinguish between two copies of one inlined variable. Take 2. 
llvm-svn: 137253
 2011-08-10 21:50:54 +00:00
Devang Patel
393d6e1fd0 While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases. 
llvm-svn: 137250
 2011-08-10 21:25:34 +00:00
Devang Patel
5a1dd582e2 Revert unintentional parts of previous check-in. 
llvm-svn: 137249
 2011-08-10 21:16:49 +00:00
Devang Patel
de73daa98c Start using LexicalScopes utility. No intetional functionality change. 
llvm-svn: 137246
 2011-08-10 20:55:27 +00:00
Jim Grosbach
e19952cfbb Fix typo. Not quite sure how that slipped in there. 
llvm-svn: 137245
 2011-08-10 20:49:18 +00:00
Jim Grosbach
bbef0044c8 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Nadav Rotem
4a8d78d24a When performing a truncating store, it is sometimes possible to rearrange the 
data in-register prior to saving to memory.  When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.

llvm-svn: 137238
 2011-08-10 19:30:14 +00:00
Devang Patel
4459f63998 Provide utility to extract and use lexical scoping information from machine instructions. 
llvm-svn: 137237
 2011-08-10 19:04:06 +00:00
Owen Anderson
0fde7a84ee Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00
Andrew Trick
c1871c7c97 Comments. Thanks for the spell check Nick! 
Also, my apologies for spoiling the autocomplete on SimplifyInstructions.cpp. I couldn't think of a better filename.

llvm-svn: 137229
 2011-08-10 18:07:05 +00:00
Bruno Cardoso Lopes
565ab1542a The following X86 pattern is incorrect: 
def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

llvm-svn: 137227
 2011-08-10 17:45:17 +00:00
Eli Friedman
fa9191bd9f Whitespace. 
llvm-svn: 137226
 2011-08-10 17:39:11 +00:00
Owen Anderson
59d627c17a Tabs --> spaces. 
llvm-svn: 137225
 2011-08-10 17:38:05 +00:00
Owen Anderson
0819cf208f Cleanups based on Nick Lewycky's feedback. 
llvm-svn: 137224
 2011-08-10 17:36:48 +00:00