Jim Grosbach
6dd5433c5c
Refactor away tSpill and tRestore pseudos in ARM backend.
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The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.
llvm-svn: 134092
2011-06-29 20:26:39 +00:00
Johnny Chen
dfac31bc1b
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
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print out ldr, not ldr.n.
rdar://problem/9267772
llvm-svn: 130008
2011-04-22 19:12:43 +00:00
Chris Lattner
0304b82f80
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Johnny Chen
443a6902bf
Thumb disassembler was erroneously rejecting "blx sp" instruction.
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rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
Johnny Chen
a4f73530a5
delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.
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llvm-svn: 128249
2011-03-25 00:17:42 +00:00
Johnny Chen
4a55a733b8
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since
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the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add
test cases for that.
llvm-svn: 128247
2011-03-24 23:42:31 +00:00
Johnny Chen
6345e6a882
The ARM disassembler was confused with the 16-bit tSTMIA instruction.
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According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.
llvm-svn: 128246
2011-03-24 23:21:14 +00:00
Johnny Chen
ae5d27987a
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
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Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
2011-03-24 20:42:48 +00:00
Jim Grosbach
a87f223848
Remove no-longer-correct special case for disasm of ARM BL instructions.
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llvm-svn: 127517
2011-03-12 01:05:29 +00:00
Jim Grosbach
daffeb06fb
Pseudo-ize the ARM 'B' instruction.
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llvm-svn: 127510
2011-03-11 23:24:15 +00:00
Jim Grosbach
2226dfbea2
Remove dead code. These ARM instruction definitions no longer exist.
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llvm-svn: 127509
2011-03-11 23:15:02 +00:00
Jim Grosbach
01a937ac07
Remove dead code. These ARM instruction definitions no longer exist.
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llvm-svn: 127508
2011-03-11 23:11:41 +00:00
Jim Grosbach
009af69d6d
Pseudo-ize VMOVDcc and VMOVScc.
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llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Jim Grosbach
b480da2317
Remove dead code. These ARM instruction definitions don't exist.
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llvm-svn: 127491
2011-03-11 20:51:07 +00:00
Jim Grosbach
ee6075cda5
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
Jim Grosbach
cb57d3b1d9
Remove dead code. These ARM instruction definitions don't exist.
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llvm-svn: 127488
2011-03-11 20:38:18 +00:00
Jim Grosbach
3329263352
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
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and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
Jim Grosbach
9cddc3746d
Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.
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llvm-svn: 127445
2011-03-11 01:16:49 +00:00
Jim Grosbach
1986d9ac8f
Properly pseudo-ize MOVCCr and MOVCCs.
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llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Jim Grosbach
41694b91ad
Memory barrier instructions don't need special handling in tblgen anymore.
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llvm-svn: 127419
2011-03-10 19:05:48 +00:00
Bob Wilson
e24bee9ce8
TableGen should not ignore BX instructions for the ARM disassembler. pr9368.
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llvm-svn: 126931
2011-03-03 07:19:52 +00:00
Bob Wilson
42f80596ca
pr9367: Add missing predicated BLX instructions.
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Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
llvm-svn: 126915
2011-03-03 01:41:01 +00:00
Owen Anderson
a2d2de33c5
Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings.
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A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.
The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.
llvm-svn: 125966
2011-02-18 21:51:29 +00:00
Bruno Cardoso Lopes
94247155c4
Add support for parsing and encoding ARM's official syntax for the BFI instruction
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llvm-svn: 123770
2011-01-18 20:45:56 +00:00
Jim Grosbach
1e943cc60d
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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llvm-svn: 121798
2010-12-14 22:28:03 +00:00
Bob Wilson
33e5e902b0
Remove the rest of the *_sfp Neon instruction patterns.
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Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
llvm-svn: 121730
2010-12-13 23:02:37 +00:00
Bill Wendling
1b8163a33e
Merge DEBUG statements.
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llvm-svn: 121660
2010-12-13 01:03:49 +00:00
Chris Lattner
8e4bbafeb3
eliminate the Records global variable, patch by Garrison Venn!
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llvm-svn: 121659
2010-12-13 00:23:57 +00:00
Jim Grosbach
ffd52cc18a
Remove reference to the CMPz instruction patterns for ARM.
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llvm-svn: 121180
2010-12-07 20:44:33 +00:00
Bill Wendling
01e67a2a03
I did it wrong. Don't disregard these encodings here.
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llvm-svn: 120786
2010-12-03 02:25:59 +00:00
Bill Wendling
fad63b8ad2
Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gpr
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instructions. They are handled as special moves, but encoded as a normal move.
llvm-svn: 120779
2010-12-03 01:55:30 +00:00
Jim Grosbach
7ae5c75ab7
The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e.,
...
no extra encoding information), so we no longer need to special case them
here.
llvm-svn: 120444
2010-11-30 19:08:32 +00:00
Jim Grosbach
6a976d0827
Tidy up.
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llvm-svn: 120443
2010-11-30 19:00:13 +00:00
Jim Grosbach
d79a0ce6e7
Delete a few no longer needed references to pseudos.
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llvm-svn: 120441
2010-11-30 18:56:13 +00:00
Jim Grosbach
89e90b7310
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
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instructions. This simplifies instruction printing and disassembly.
llvm-svn: 120333
2010-11-29 22:37:40 +00:00
Jim Grosbach
71042b51a1
Rename t2 TBB and TBH instructions to reference that they encode the jump table
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data. Next up, pseudo-izing them.
llvm-svn: 120320
2010-11-29 21:28:32 +00:00
Michael J. Spencer
d5ec932c3a
Merge System into Support.
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llvm-svn: 120298
2010-11-29 18:16:10 +00:00
Bill Wendling
b450d320ec
Encode the multi-load/store instructions with their respective modes ('ia',
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'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
Chris Lattner
45b1a1649c
factor the operand list (and related fields/operations) out of
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CodeGenInstruction into its own helper class. No functionality change.
llvm-svn: 117893
2010-11-01 04:03:32 +00:00
Jim Grosbach
fb59963159
A few 80 column cleanups
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llvm-svn: 116069
2010-10-08 18:13:57 +00:00
Jim Grosbach
504d7b7d8b
Move checking for t2MOVCCi16 to the right place.
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llvm-svn: 115994
2010-10-07 22:14:01 +00:00
Nick Lewycky
2d8ea609e1
Fix typo in comment.
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llvm-svn: 115986
2010-10-07 21:55:16 +00:00
Jim Grosbach
c0a61c0796
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
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llvm-svn: 115890
2010-10-07 00:53:56 +00:00
Jim Grosbach
1e2566c20d
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
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llvm-svn: 115884
2010-10-07 00:42:42 +00:00
Jim Grosbach
04a4f7c5d9
Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling.
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llvm-svn: 115841
2010-10-06 21:17:07 +00:00
Bob Wilson
d107dd5cd2
Fix a comment typo.
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llvm-svn: 112302
2010-08-27 21:56:59 +00:00
Bob Wilson
0650cceb38
Add a separate ARM instruction format for Saturate instructions.
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(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
llvm-svn: 110754
2010-08-11 00:01:18 +00:00
Dale Johannesen
2df647f882
Changes to ARM tail calls, mostly cosmetic.
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Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
llvm-svn: 107851
2010-07-08 01:18:23 +00:00
Dale Johannesen
81914dea4e
An attempt to fix the problem Anton reported with
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ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
llvm-svn: 106309
2010-06-18 20:44:28 +00:00