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Commit Graph

20176 Commits

Author SHA1 Message Date
Rafael Espindola
6fe0d5f4be Add -disable-debug-info-verifier to a RUN line.
Found by running the test with pipefail enabled.

llvm-svn: 187046
2013-07-24 14:56:31 +00:00
Chandler Carruth
97ac149a21 Fix a problem I introduced in r187029 where we would over-eagerly
schedule an alloca for another iteration in SROA. This only showed up
with a mixture of promotable and unpromotable selects and phis. Added
a test case for this.

llvm-svn: 187031
2013-07-24 12:12:17 +00:00
Chandler Carruth
b086f93d75 Fix PR16687 where we were incorrectly promoting an alloca that had
pending speculation for a phi node. The problem here is that we were
using growth of the specluation set as an indicator of whether
speculation would occur, and if the phi node is already in the set we
don't see it grow. This is a symptom of the fact that this signal is
a total hack.

Unfortunately, I couldn't really come up with a non-hacky way of
signaling that promotion remains valid *after* speculation occurs, such
that we only speculate when all else looks good for promotion. In the
end, I went with at least a much more explicit approach of doing the
work of queuing inside the phi and select processing and setting
a preposterously named flag to convey that we're in the special state of
requiring speculating before promotion.

Thanks to Richard Trieu and Nick Lewycky for the excellent work reducing
a testcase for this from a pretty giant, nasty assert in a big
application. =] The testcase was excellent.

llvm-svn: 187029
2013-07-24 09:47:28 +00:00
Manman Ren
9438f9191a Update testing cases to make them pass debug info verification.
llvm-svn: 187016
2013-07-24 01:26:37 +00:00
Tom Stellard
cf58aac74c DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free
This commit also implements these functions for R600 and removes a test
case that was relying on the buggy behavior.

llvm-svn: 187007
2013-07-23 23:55:03 +00:00
Tom Stellard
7e06ca2a39 R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary
These are really the same address space in hardware.  The only
difference is that CONSTANT_ADDRESS uses a special cache for faster
access.  When we are unable to use the constant kcache for some reason
(e.g. smaller types or lack of indirect addressing) then the instruction
selector must use GLOBAL_ADDRESS loads instead.

llvm-svn: 187006
2013-07-23 23:54:56 +00:00
Manman Ren
35c74ac066 Debug Info: improve the Finder.
Improve the Finder to handle context of a DIVariable.
If Scope is a DICompileUnit, add it to the list of CUs.

llvm-svn: 187003
2013-07-23 23:10:00 +00:00
Quentin Colombet
995760ffc1 [ARM][ISel] Improve the lowering of vector loads.
When vectors are built from a single value, the ARM lowering issues a
scalar_to_vector node.
This node is then always morphed into a move from the general purpose unit to
the vector unit.
When the value comes from a load, this can be simplified into a vector load to
the right lane.

This patch changes the lowering of insert_vector_elt to expose a vector
friendly pattern in this situation.

This is a step toward fixing <rdar://problem/14170854>.

llvm-svn: 186999
2013-07-23 22:34:47 +00:00
Rafael Espindola
cc9afb9150 Add not so that these tests pass with pipefail enabled.
llvm-svn: 186939
2013-07-23 13:18:20 +00:00
Rafael Espindola
f71859b862 Add -disable-debug-info-verifier.
Found while testing with pipefail enabled.

llvm-svn: 186937
2013-07-23 12:31:37 +00:00
Rafael Espindola
081f6f185f Add an initial implementation of archive symbol table generation.
The symbol table has forward references in the file. Instead of allocating
a temporary buffer or counting the size and then writing, this implementation
writes a dummy value first and patches it once the final value is known.

There is room for performance improvement. I will implement them as soon as I
get some other features (like a ranlib mode) in.

llvm-svn: 186934
2013-07-23 10:47:01 +00:00
NAKAMURA Takumi
8a95447142 llvm/test/DebugInfo/X86/dbg-value-range.ll: Add -disable-debug-info-verifier, too, since r186902.
llvm-svn: 186930
2013-07-23 06:41:51 +00:00
Craig Topper
c7bcbfdf42 Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
llvm-svn: 186924
2013-07-23 01:50:47 +00:00
Tom Stellard
e096e3c298 R600: Add support for 24-bit MAD instructions
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186923
2013-07-23 01:48:49 +00:00
Tom Stellard
803a4c6e50 R600: Add support for 24-bit MUL instructions
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186922
2013-07-23 01:48:42 +00:00
Tom Stellard
705721da31 R600: Improve support for < 32-bit loads
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186921
2013-07-23 01:48:35 +00:00
Tom Stellard
bc9deba8ad R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()
This increases the number of opportunites we have for folding.  With the
previous implementation we were unable to fold into any instructions
other than the first when multiple instructions were selected from a
single SDNode.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186919
2013-07-23 01:48:24 +00:00
Tom Stellard
e60bb5f272 R600: Use KCache for kernel arguments
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186918
2013-07-23 01:48:18 +00:00
Tom Stellard
6ca248c89f R600: Use the same compute kernel calling convention for all GPUs
A side-effect of this is that now the compiler expects kernel arguments
to be 4-byte aligned.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186916
2013-07-23 01:48:05 +00:00
Tom Stellard
ac10764020 R600: Use correct LoadExtType when lowering kernel arguments
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186915
2013-07-23 01:47:58 +00:00
Tom Stellard
d7dd88a3f7 R600: Clean up extended load patterns
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186914
2013-07-23 01:47:52 +00:00
Tom Stellard
25ce190913 R600: Expand vector FNEG
llvm-svn: 186913
2013-07-23 01:47:46 +00:00
Manman Ren
3a6f508b6b Debug Info Finder: use processDeclare and processValue to list debug info
MDNodes used by DbgDeclareInst and DbgValueInst.

Another 16 testing cases failed and they are disabled with
-disable-debug-info-verifier.
A total of 34 cases are disabled with -disable-debug-info-verifier and will be
corrected.

llvm-svn: 186902
2013-07-23 00:22:51 +00:00
Nadav Rotem
383f980dca When we vectorize across multiple basic blocks we may vectorize PHINodes that create a cycle. We already break the cycle on phi-nodes, but arithmetic operations are still uplicated. This patch adds code that checks if the operation that we are vectorizing was vectorized during the visit of the operands and uses this value if it can.
llvm-svn: 186883
2013-07-22 22:18:07 +00:00
Kevin Enderby
4f4de8ba04 Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221

llvm-svn: 186878
2013-07-22 21:25:31 +00:00
Jakub Staszak
ba65057867 Fix typo in test.
llvm-svn: 186876
2013-07-22 21:10:42 +00:00
Craig Topper
86b83be14d Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
llvm-svn: 186869
2013-07-22 20:46:37 +00:00
Bill Wendling
63482ebdd5 Recommit r186217 with testcase fix:
Use the function attributes to pass along the stack protector buffer size.

 Now that we have robust function attributes, don't use a command line option to
 specify the stack protecto buffer size.

llvm-svn: 186863
2013-07-22 20:15:21 +00:00
Akira Hatanaka
39a746e93f [mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861
2013-07-22 19:30:38 +00:00
Rafael Espindola
b5df8607a3 Mark ELF's first symbol as format specific so that llvm-nm ignores it.
llvm-svn: 186860
2013-07-22 19:24:34 +00:00
Akira Hatanaka
9f2c66ce7c [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855
2013-07-22 18:52:22 +00:00
Mihai Popa
cb970f1789 This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:

1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset

llvm-svn: 186831
2013-07-22 15:49:36 +00:00
Rafael Espindola
9cfbdad631 Replace archive members in the old position.
This matches gnu archive behavior and since archive member order can change
which member is used, not changing the order on replacement looks like the
right thing to do.

This patch also refactors the logic for which archive member to keep and
whether to move it to a helper function (computeInsertAction). The
nesting in computeNewArchiveMembers was getting a bit confusing.

llvm-svn: 186829
2013-07-22 15:11:51 +00:00
Rafael Espindola
ce62c0a883 Don't depend on a llvm-ar specific behavior.
GNU ar when not given the a or b modifiers replaces archive members in the
same location of the old ones. I am about to implement that in llvm-ar. For
now, just don't depend on the current llvm-ar behavior on this test.

llvm-svn: 186823
2013-07-22 12:41:04 +00:00
Justin Holewinski
0a7b783785 [NVPTX] Use approximate FP ops when unsafe-fp-math is used, and append
.ftz to instructions if the nvptx-f32ftz attribute is set to "true"

llvm-svn: 186820
2013-07-22 12:18:04 +00:00
Richard Smith
15b9b9e375 Treat nothrow forms of ::operator delete and ::operator delete[] as
deallocation functions.

llvm-svn: 186798
2013-07-21 23:11:42 +00:00
Rafael Espindola
c2acfa8f64 Handle replacement into a position past the original member.
We were incorrectly computing where to insert a member if it was replacing
a previous member that was before the insert point.

llvm-svn: 186792
2013-07-21 12:58:07 +00:00
Rafael Espindola
b64a8ded32 Don't crash when llvm.compiler.used becomes empty.
GlobalOpt simplifies llvm.compiler.used by removing any members that are also
in the more strict llvm.used. Handle the special case where llvm.compiler.used
becomes empty.

llvm-svn: 186778
2013-07-20 23:33:15 +00:00
Matt Arsenault
ff6bd087c7 Disallow global aliases to bitcast between address spaces
llvm-svn: 186767
2013-07-20 17:46:05 +00:00
Stephen Lin
5a583ae2f7 InstCombine: call FoldOpIntoSelect for all floating binops, not just fmul
llvm-svn: 186759
2013-07-20 07:13:13 +00:00
Matt Arsenault
47a9a42835 Have InlineCost check constant fcmps
llvm-svn: 186758
2013-07-20 04:09:00 +00:00
Lang Hames
2d3b19969c Refactor AnalyzeBranch on ARM. The previous version did not always analyze
indirect branches correctly. Under some circumstances, this led to the deletion
of basic blocks that were the destination of indirect branches. In that case it
left indirect branches to nowhere in the code.

This patch replaces, and is more general than either of the previous fixes for
indirect-branch-analysis issues, r181161 and r186461.

For other branches (not indirect) this refactor should have *almost* identical
behavior to the previous version. There are some corner cases where this
refactor is able to analyze blocks that the previous version could not (e.g.
this necessitated the update to thumb2-ifcvt2.ll). 

<rdar://problem/14464830>

llvm-svn: 186735
2013-07-19 23:52:47 +00:00
Rui Ueyama
f2baef0d6e Retry submitting r186623: COFFDumper: Dump data directory entries.
The original change was rolled back in r186627 because of test
failures on the big endian machine. I believe I fixed the issue
so re-submitting.

llvm-svn: 186734
2013-07-19 23:23:29 +00:00
Vincent Lejeune
946e631d0f R600: Don't emit empty then clause and use alu_pop_after
llvm-svn: 186725
2013-07-19 21:45:15 +00:00
Rafael Espindola
e054c779bd Fix inserting new elements in a specified location.
We were only handling the 'a' and 'b' options during moves before.

llvm-svn: 186721
2013-07-19 21:23:28 +00:00
Rafael Espindola
6178a47aa5 s/compiler_used/compiler.used/.
We were incorrectly using compiler_used instead of compiler.used. Unfortunately
the passes using the broken name had tests also using the broken name.

llvm-svn: 186705
2013-07-19 18:44:51 +00:00
Richard Sandiford
49d61a017c [SystemZ] Add tests for ALHSIK and ALGHSIK
The insn definitions themselves crept into r186689, sorry.
This should be the last of the distinct-ops instructions.

llvm-svn: 186690
2013-07-19 16:44:32 +00:00
Richard Sandiford
fe2faa0d5b [SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.

llvm-svn: 186689
2013-07-19 16:37:00 +00:00
Joey Gouly
cfa16b3bc1 [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
llvm-svn: 186688
2013-07-19 16:34:16 +00:00
Richard Sandiford
8ae3d3dbfc [SystemZ] Add AHIK and AGHIK
I did these as a separate patch because it uses a slightly different
form of RIE layout.

llvm-svn: 186687
2013-07-19 16:32:12 +00:00