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7017e6a466
Commit Graph

1796 Commits

Author SHA1 Message Date
Reed Kotler
7017e6a466 Add an omitted IsCall=1. 
llvm-svn: 187553
 2013-08-01 00:59:06 +00:00
Akira Hatanaka
5651fa36f7 [mips] Rename instruction DANDi to ANDi64. 
No functionality change.

llvm-svn: 187469
 2013-07-31 00:57:41 +00:00
Akira Hatanaka
d0c19bc118 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.

llvm-svn: 187468
 2013-07-31 00:55:34 +00:00
Akira Hatanaka
9f04532f39 [mips] Delete instruction format for "bal". 
llvm-svn: 187443
 2013-07-30 20:42:19 +00:00
Akira Hatanaka
00e403d37b [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that 
turns "bal" into "bgezal".

llvm-svn: 187440
 2013-07-30 20:24:24 +00:00
Vladimir Medic
aafcb477fd This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. 
llvm-svn: 187410
 2013-07-30 10:12:14 +00:00
Akira Hatanaka
591151f071 [mips] Add comment and simplify function. 
llvm-svn: 187371
 2013-07-29 19:08:34 +00:00
Akira Hatanaka
329763d851 [mips] Implement llvm.trap intrinsic. 
Patch by Sasa Stankovic.

llvm-svn: 187244
 2013-07-26 20:58:55 +00:00
Akira Hatanaka
689acaf88f [mips] Fix FP conditional move instructions to have explicit FP condition code 
register operands.

llvm-svn: 187242
 2013-07-26 20:51:20 +00:00
Akira Hatanaka
35c6208a5a [mips] Fix FP branch instructions to have explicit FP condition code register 
operands.

llvm-svn: 187238
 2013-07-26 20:13:47 +00:00
Akira Hatanaka
6e2705a339 [mips] Increase the number of floating point condition code registers to eight. 
llvm-svn: 187234
 2013-07-26 19:03:48 +00:00
Akira Hatanaka
e6ef926882 [mips] Fix floating point branch, comparison, and conditional move instructions 
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.

llvm-svn: 187233
 2013-07-26 19:01:56 +00:00
Akira Hatanaka
f96ca1bdd3 [mips] Delete register print method MipsInstPrinter::printCPURegs that is not 
needed. The generic method printOperand will do.

No functionality change.

llvm-svn: 187231
 2013-07-26 18:50:42 +00:00
Akira Hatanaka
66dcf905b6 [mips] Print instructions "beq", "bne" and "or" using assembler pseudo 
instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3

llvm-svn: 187229
 2013-07-26 18:34:25 +00:00
Akira Hatanaka
6132f6bc57 [mips] Make MipsAsmParser::parseCCRRegs return NoMatch instead of ParseFail 
when there wasn't a match. This behavior is consistent with other register
parsing methods.

llvm-svn: 187063
 2013-07-24 18:43:52 +00:00
Petar Jovanovic
22aad9fa66 [test commit] Minor comment change. 
Testing commit access credentials.

llvm-svn: 187032
 2013-07-24 13:02:35 +00:00
Craig Topper
9bf1d910c8 Split generated asm mnemonic matching table into a separate table for each asm variant. 
This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.

llvm-svn: 187026
 2013-07-24 07:33:14 +00:00
Akira Hatanaka
39a746e93f [mips] Fix MipsAsmParser::parseCCRRegs. 
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861
 2013-07-22 19:30:38 +00:00
Akira Hatanaka
9f2c66ce7c [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete 
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855
 2013-07-22 18:52:22 +00:00
Akira Hatanaka
e50f645c46 [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR. 
No functionality change.

llvm-svn: 186642
 2013-07-19 01:19:52 +00:00
Vladimir Medic
0a645b02e5 This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch. 
llvm-svn: 186567
 2013-07-18 09:28:35 +00:00
Akira Hatanaka
55be054f1e [mips] Use "foreach" loop to make register definitions more concise. 
llvm-svn: 186528
 2013-07-17 19:09:27 +00:00
Vladimir Medic
3b0689d2d1 This patch checks for valid mnemonics at the beginning of parseInstruction method, thus giving the user the right error message for non-existing instructions. 
llvm-svn: 186512
 2013-07-17 15:00:42 +00:00
Vladimir Medic
d22167f3e0 Implement eret and deret(return from exception) instructions for Mips. Test examples are given. 
llvm-svn: 186507
 2013-07-17 14:05:19 +00:00
Juergen Ributzka
9f40835ba8 Test commit to verify write access. 
llvm-svn: 186429
 2013-07-16 17:44:23 +00:00
Vladimir Medic
a067a86f5e Fixing a buildbot failure:unused function. 
llvm-svn: 186403
 2013-07-16 11:43:20 +00:00
Vladimir Medic
e3aeddca47 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. 
llvm-svn: 186397
 2013-07-16 10:07:14 +00:00
Craig Topper
58fa7a9b4a Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 
llvm-svn: 186274
 2013-07-14 04:42:23 +00:00
Akira Hatanaka
6f48f304ac [mips] Implement MipsTargetMachine::getInstrItineraryData(). 
llvm-svn: 186227
 2013-07-12 23:33:22 +00:00
Akira Hatanaka
b94a7de0c8 [mips] Add instruction itinerary classes for mult, seb and slt instructions. 
llvm-svn: 186222
 2013-07-12 22:43:20 +00:00
Vladimir Medic
8e12e22a4d Add support for Mips break and syscall insructions. The corresponding test cases are added. 
llvm-svn: 186151
 2013-07-12 09:25:35 +00:00
Vladimir Medic
d4a8ab4928 Reverting commit r185999 due to buildboot failure. 
llvm-svn: 186000
 2013-07-10 12:26:26 +00:00
Vladimir Medic
408af148a4 Add support for Mips break and syscall insructions. The corresponding test cases are added. 
llvm-svn: 185999
 2013-07-10 10:18:10 +00:00
Jakob Stoklund Olesen
d428205e4a Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

llvm-svn: 185625
 2013-07-04 13:54:20 +00:00
Craig Topper
783617eba7 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. 
llvm-svn: 185606
 2013-07-04 01:31:24 +00:00
Jakob Stoklund Olesen
8099b21497 Revert r185595-185596 which broke buildbots. 
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

llvm-svn: 185600
 2013-07-04 00:26:30 +00:00
Jakob Stoklund Olesen
8bc33424b2 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

llvm-svn: 185596
 2013-07-03 23:56:31 +00:00
Craig Topper
9729e843cb Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. 
llvm-svn: 185540
 2013-07-03 15:07:05 +00:00
Akira Hatanaka
1b1f481a6c [mips] Add new InstrItinClasses for move from/to coprocessor instructions and 
floating point loads and stores.

No changes in functionality.

llvm-svn: 185399
 2013-07-02 00:00:02 +00:00
Akira Hatanaka
c5fa7b5e51 [mips] Reverse the order of source operands of shift and rotate instructions that 
have three register operands.

No intended functionality changes.

llvm-svn: 185376
 2013-07-01 20:39:53 +00:00
Akira Hatanaka
3787fb8dc0 [mips] Increase the number of floating point control registers available to 32. 
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.

llvm-svn: 185373
 2013-07-01 20:31:44 +00:00
Chad Rosier
2b164134e8 [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg 
function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.

llvm-svn: 185026
 2013-06-26 22:23:32 +00:00
Akira Hatanaka
677f305c97 [mips] Do not emit ".option pic0" if target is mips64. 
llvm-svn: 185012
 2013-06-26 19:08:49 +00:00
Akira Hatanaka
1f2c22ad07 [mips] Improve code generation for constant multiplication using shifts, adds and 
subs.

llvm-svn: 185011
 2013-06-26 18:48:17 +00:00
Vladimir Medic
4c032a5386 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. 
llvm-svn: 184716
 2013-06-24 10:05:34 +00:00
Chad Rosier
d00211e479 The getRegForInlineAsmConstraint function should only accept MVT value types. 
llvm-svn: 184642
 2013-06-22 18:37:38 +00:00
Vladimir Medic
af5979fc83 Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers. 
llvm-svn: 184411
 2013-06-20 11:21:49 +00:00
Bill Wendling
a9576dc938 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
llvm-svn: 184360
 2013-06-19 21:36:55 +00:00
Vladimir Medic
10551de6bd The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp 
llvm-svn: 184292
 2013-06-19 10:14:36 +00:00
Jack Carter
016185840e Mips ELF: Mark object file as ABI compliant 
When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore

llvm-svn: 184220
 2013-06-18 19:47:15 +00:00