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Commit Graph

158342 Commits

Author SHA1 Message Date
Craig Topper
7c5027d178 [X86] Minor formatting fix to getHostCPUFeatures. NFC
llvm-svn: 321015
2017-12-18 19:40:11 +00:00
Jessica Paquette
ffb43a84c6 [MachineOutliner] Recommit r320229
LR was undefined entering outlined functions that contain calls. This made the
machine verifier unhappy when expensive checks were enabled. This fixes that.

llvm-svn: 321014
2017-12-18 19:33:21 +00:00
Benjamin Kramer
b502174415 [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.
This has the same issue as the early pass disabled in r321010.

llvm-svn: 321013
2017-12-18 19:21:56 +00:00
Don Hinton
d4b6dda211 [cmake] Update experimental target error message
Summary:
Update this error message indicate this test only ensures experimental
targets were passed via LLVM_EXPERIMENTAL_TARGETS_TO_BUILD.

Originally, this test validated all targets, but in r184923, it was moved
after the LLVMBUILDTOOL test, which also validates all targets, making
that part of the test redundant.

Differential Revision: https://reviews.llvm.org/D41273

llvm-svn: 321012
2017-12-18 19:15:15 +00:00
Paul Robinson
6c98a1197f Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."
Adds missing support for DW_FORM_data16.

Update of r320852/r320886, fixing the unittest again, this time use a
raw char string for the test data.

Differential Revision: https://reviews.llvm.org/D41090

llvm-svn: 321011
2017-12-18 19:08:35 +00:00
Benjamin Kramer
4212c01ddc [PPC] Disable reg+reg to reg+imm transformation.
It creates invalid instructions. PR35688.

llvm-svn: 321010
2017-12-18 18:56:57 +00:00
Dimitry Andric
4fc5ef9136 Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC.
llvm-svn: 321009
2017-12-18 18:56:00 +00:00
Krzysztof Parzyszek
12c1e37aed [Hexagon] Higher versions of HVX imply presence of lower versions
The code in Hexagon_MC::completeHVXFeatures wasn't setting all HVX-
related features correctly.

llvm-svn: 321008
2017-12-18 18:51:57 +00:00
Ivan A. Kosarev
d288ed2ca2 [IR] Support the new TBAA metadata format in IR verifier
Differential Revision: https://reviews.llvm.org/D40438

llvm-svn: 321007
2017-12-18 18:46:44 +00:00
Dimitry Andric
ed6078b4c3 Fix inconsistent line endings in ARCDisassembler.cpp. NFC.
llvm-svn: 321006
2017-12-18 18:45:37 +00:00
Krzysztof Parzyszek
26809b946a i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004
llvm-svn: 321005
2017-12-18 18:41:52 +00:00
Krzysztof Parzyszek
cfecd633ca [Hexagon] Generate HVX code for vector sign-, zero- and any-extends
Implement any-extend as zero-extend.

llvm-svn: 321004
2017-12-18 18:32:27 +00:00
Simon Pilgrim
71664d85c4 [X86] Regenerate test to improve codegen testing for D41350
llvm-svn: 321003
2017-12-18 18:31:02 +00:00
Krzysztof Parzyszek
9aac18c5f6 [Hexagon] Prefer to widen HVX vectors instead of promoting
llvm-svn: 321002
2017-12-18 18:21:01 +00:00
Matt Arsenault
573b805c7a Removed unused DominanceFrontier
llvm-svn: 321001
2017-12-18 18:01:13 +00:00
Teresa Johnson
446d067392 [ThinLTO] Make distributed indexes test more robust
Modify test so that it passes in the reverse-iteration bot.
We use DenseMap instead of std::map for the summaries to emit into
distributed index files. The iteration order is not defined, but
it is deterministic, which is good enough.

llvm-svn: 321000
2017-12-18 18:00:32 +00:00
Xinliang David Li
119265e2c4 [PGO] add MST min edge selection heuristic to ensure non-zero entry count
Differential Revision: http://reviews.llvm.org/D41059

llvm-svn: 320998
2017-12-18 17:56:19 +00:00
Francis Visoiu Mistrih
061acf9c7f [YAML] Add support for non-printable characters
LLVM IR function names which disable mangling start with '\01'
(https://www.llvm.org/docs/LangRef.html#identifiers).

When an identifier like "\01@abc@" gets dumped to MIR, it is quoted, but
only with single quotes.

http://www.yaml.org/spec/1.2/spec.html#id2770814:

"The allowed character range explicitly excludes the C0 control block
allowed), the surrogate block #xD800-#xDFFF, #xFFFE, and #xFFFF."

http://www.yaml.org/spec/1.2/spec.html#id2776092:

"All non-printable characters must be escaped.
[...]
Note that escape sequences are only interpreted in double-quoted scalars."

This patch adds support for printing escaped non-printable characters
between double quotes if needed.

Should also fix PR31743.

Differential Revision: https://reviews.llvm.org/D41290

llvm-svn: 320996
2017-12-18 17:38:03 +00:00
Ivan A. Kosarev
3b753d324c [IR] Add MDBuilder helpers for the new TBAA metadata format
The new helpers are supposed to be used in clang to generate TBAA
information in the new format proposed in this thread:

http://lists.llvm.org/pipermail/llvm-dev/2017-November/118748.html

Differential Revision: https://reviews.llvm.org/D39956

llvm-svn: 320993
2017-12-18 16:49:39 +00:00
Sander de Smalen
d0e69f2111 [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specified
Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified.

Reviewers: rengolin, fhahn, olista01, echristo, efriedma

Reviewed By: fhahn

Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40363

llvm-svn: 320992
2017-12-18 16:48:53 +00:00
Simon Dardis
848b9e1f1f Reland "[mips] Fix the target specific instruction verifier"
Fix an off by one error in the bounds checking for 'dinsu' and update
the ranges in the test comments so that they are accurate.

This version has the correct commit message.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D41183

llvm-svn: 320991
2017-12-18 15:56:40 +00:00
Sean Fertile
82dc63b9f5 [Memcpy Loop Lowering] Remove the fixed int8 lowering.
Switch over to the lowering that uses target supplied operand types.

Differential Revision: https://reviews.llvm.org/D41201

llvm-svn: 320989
2017-12-18 15:31:14 +00:00
Sander de Smalen
332291dd3b [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction
Summary:
When emitting a diagnostic for an invalid operand, a specific diagnostic
should only be reported when the instruction being matched is actually
enabled by the feature flags.

Patch [3/4] in a series to add parsing of predicates and properly parse SVE 
ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when
the SVE feature is not specified.

Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund

Reviewed By: olista01, sdardis

Subscribers: fhahn, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40362

llvm-svn: 320986
2017-12-18 14:34:24 +00:00
Max Kazantsev
a73d76d8be [LVI] Support for ashr in LVI
Enhance LVI to analyze the ‘ashr’ binary operation. This leverages the infrastructure in ConstantRange for the ashr operation.

Patch by Surya Kumari Jangala!

Differential Revision: https://reviews.llvm.org/D40886

llvm-svn: 320983
2017-12-18 14:23:30 +00:00
Diana Picus
2db9c43832 [ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524
r319524 has made more G_MERGE_VALUES/G_UNMERGE_VALUES pairs legal than
are supported by the rest of the pipeline. Restrict that to only the
cases that we can currently handle: packing 32-bit values into 64-bit
ones, when we have hardware FP.

llvm-svn: 320980
2017-12-18 13:22:28 +00:00
Benjamin Kramer
0ecb4b1883 Constexprify LaneBitmask factory methods.
This avoids global constructors when they're used in a global constant.

llvm-svn: 320979
2017-12-18 13:20:26 +00:00
Max Kazantsev
104b1b7894 [ConstantRange] Support for ashr in ConstantRange computation
Extend the ConstantRange implementation to compute the range of possible values resulting from an arithmetic right shift operation.
There will be a follow up patch to leverage this constant range infrastructure in LazyValueInfo.

Patch by Surya Kumari Jangala!

Differential Revision: https://reviews.llvm.org/D40881

llvm-svn: 320976
2017-12-18 13:01:32 +00:00
Simon Dardis
125dd707fa Revert "[mips] Fix the target specific instruction verifier"
This reverts commit r320974. The commit message lacked the Differential Revison: line.

llvm-svn: 320975
2017-12-18 12:30:34 +00:00
Simon Dardis
91a35077f1 [mips] Fix the target specific instruction verifier
Fix an off by one error in the bounds checking for 'dinsu' and update
the ranges in the test comments so that they are accurate.

Reviewers: atanasyan

https://reviews.llvm.org/D41183

llvm-svn: 320974
2017-12-18 12:24:17 +00:00
Sander de Smalen
5db6217e15 [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)
Summary: Patch [2/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.

Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro

Reviewed By: fhahn

Subscribers: aemerson, javed.absar, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D40361

llvm-svn: 320973
2017-12-18 11:29:59 +00:00
Sander de Smalen
fea381d052 [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support
Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.

Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma

Reviewed By: fhahn

Subscribers: aemerson, javed.absar, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D40360

llvm-svn: 320970
2017-12-18 11:26:34 +00:00
Eugene Leviant
d93be42171 [ThinLTO] Remove unused code
This is a re-commit of r320464, after patch for gold plugin
was landed.

llvm-svn: 320968
2017-12-18 10:53:45 +00:00
Tim Northover
173215fc06 AArch64: work around how Cyclone handles "movi.2d vD, #0".
For Cylone, the instruction "movi.2d vD, #0" is executed incorrectly in some rare
circumstances. Work around the issue conservatively by avoiding the instruction entirely.

This patch changes CodeGen so that problematic instructions are never
generated, and the AsmParser so that an equivalent instruction is used (with a
warning).

llvm-svn: 320965
2017-12-18 10:36:00 +00:00
Igor Laevsky
1579bc58b7 [TargetLibraryInfo] Discard library functions with incorrectly sized integers
Differential Revision: https://reviews.llvm.org/D41184

llvm-svn: 320964
2017-12-18 10:31:58 +00:00
Sam Parker
be148bfe75 [ARM] Adjust test checks
Correct the CHECK-LABELS of a couple of dag combine tests.

llvm-svn: 320963
2017-12-18 10:08:03 +00:00
Sam Parker
8d37a4ad46 [DAGCombine] Move AND nodes to multiple load leaves
Search from AND nodes to find whether they can be propagated back to
loads, so that the AND and load can be combined into a narrow load.
We search through OR, XOR and other AND nodes and all bar one of the
leaves are required to be loads or constants. The exception node then
needs to be masked off meaning that the 'and' isn't removed, but the
loads(s) are narrowed still.

Differential Revision: https://reviews.llvm.org/D41177

llvm-svn: 320962
2017-12-18 10:04:27 +00:00
Clement Courbet
6b3db4c125 [NFC][CodeGen][ExpandMemCmp] Fix documentation.
llvm-svn: 320960
2017-12-18 07:32:48 +00:00
Craig Topper
ac388f76eb [X86] Use mattr instead of mcpu in some of the cost model tests.
Based on the names of the check lines, features seems more appropriate that cpu.

Spotted while prototyping my patch to make 512-bit vectors illegal on SKX sometimes.

llvm-svn: 320959
2017-12-18 07:21:58 +00:00
Hiroshi Inoue
8deb4ec34f [SROA] Disable non-whole-alloca splits by default
This patch introduce a switch to control splitting of non-whole-alloca slices with default off.
The switch will be default on again after fixing an issue reported in PR35657.

llvm-svn: 320958
2017-12-18 06:47:37 +00:00
Craig Topper
0e3800880f [X86] Fix mistake that I made when splitting up the setOperationAction calls recently.
The block I moved things that need BWI and 512-bit or VLX is incorrectly qualified with just hasBWI || hasVLX. Here I've qualified it with hasBWI && (hasAVX512 || hasVLX) where the hasAVX512 will be replaced with allowing 512-bit vectors in an upcoming patch.

llvm-svn: 320957
2017-12-18 04:50:05 +00:00
Serguei Katkov
fb3e2e6057 [CGP] Fix the handling select inst in complex addressing mode
When we put the value in select placeholder we must pass
the value through simplification tracker due to the value might
be already simplified and erased.

This is a fix for PR35658.

Reviewers: john.brawn, uabelho
Reviewed By: john.brawn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41251

llvm-svn: 320956
2017-12-18 04:25:07 +00:00
Sanjay Patel
2b28c31ebe [x86] add tests for finite libcall lowering (PR35672); NFC
llvm-svn: 320955
2017-12-18 00:38:45 +00:00
Bjorn Steinbrink
6c4aa2e994 Re-commit "Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes()""
llvm-clang-x86_64-expensive-checks-win is still broken, so the failure
seems unrelated.

llvm-svn: 320953
2017-12-17 21:20:16 +00:00
Craig Topper
a9597e66b9 [X86] Add test cases that show cases where buildvector of extract and inserts should be turned into fmsubadd.
This is a follow up to the fmaddsub support added in r320950. Hopefully in the future we can fix lowering to handle this fmsubadd too.

llvm-svn: 320951
2017-12-17 18:31:36 +00:00
Craig Topper
e2c462fd3c [X86] Make the code that creates fmaddsub from build_vector of extracts and inserts functional and add tests.
Summary:
We had no tests for this and we couldn't do the optimization because of a bad use count check. We need to know how many non-undef pieces of the build vector were filled in and ensure our use count is equal to that. But on the shuffle combine version we need the use count to be 2.

The missing coverage was noticed during the review of D40335.

Reviewers: RKSimon, zvi, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41133

llvm-svn: 320950
2017-12-17 18:23:45 +00:00
Simon Pilgrim
c2260b2954 [X86] Regenerate truncated rotation tests + add missing 32-bit checks
llvm-svn: 320949
2017-12-17 18:20:42 +00:00
Sam Clegg
8e89fc161d use uint32_t
llvm-svn: 320947
2017-12-17 17:50:07 +00:00
Sam Clegg
ab1634c78c [WebAssembly] Export some more info on wasm funtions
Summary:
These fields are useful for lld's gc-sections support

Also remove an unused field.

Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish

Differential Revision: https://reviews.llvm.org/D41320

llvm-svn: 320946
2017-12-17 17:50:07 +00:00
Bjorn Steinbrink
fc60f58a3f Revert "Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes()"
This reverts commit 217067d5179882de9deb60d2e866befea4c126e7.

Fails on llvm-clang-x86_64-expensive-checks-win

llvm-svn: 320945
2017-12-17 15:16:58 +00:00
Bjorn Steinbrink
65ee49e8fb Revert "Treat sret arguments as being dereferenceable in getPointerDereferenceableBytes()"
This reverts commit 8b7a7660a3904b2088bc594311bcea2c651def08.

I didn't mean to commit this.

llvm-svn: 320944
2017-12-17 15:16:51 +00:00