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Commit Graph

97374 Commits

Author SHA1 Message Date
Daniel Sanders
7197569bdb [mips][msa] Fix buildbot failures caused by an unused variable when assertions are disabled.
llvm-svn: 194472
2013-11-12 11:14:18 +00:00
Daniel Sanders
8932f5bd6d [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)
llvm-svn: 194471
2013-11-12 10:45:18 +00:00
Bradley Smith
d0276d3c63 [ARM] Add support for FP_HP_extension build attribute
llvm-svn: 194470
2013-11-12 10:38:05 +00:00
Daniel Sanders
464a7ad75b [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics)
llvm-svn: 194469
2013-11-12 10:31:49 +00:00
Daniel Sanders
dc0cf6755d [mips][msa] Change constant used in ori tests to avoid conflict with bseti (also xori to avoid bnegi)
Upcoming commit(s) are going to add support for bseti and bnegi. This would
cause some existing tests to (correctly) change behaviour and emit a different
instruction. This patch prevents this by changing the constant used in ori and
xori tests so that they will not be matchable by the bseti and bnegi patterns
when these instructions are matchable from normal IR.

llvm-svn: 194467
2013-11-12 10:14:18 +00:00
Robert Lytton
3962d1cdf0 XCore target: fix bug in aligning 'byval i8*' on the stack
llvm-svn: 194466
2013-11-12 10:11:35 +00:00
Robert Lytton
7bf99af88b XCore target test for hidden declaration
llvm-svn: 194465
2013-11-12 10:11:30 +00:00
Robert Lytton
584459d7ea Add XCore support for ATOMIC_FENCE.
ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There
is no need to emit an instructions since the XCore provides sequential
consistency.

Original patch by Richard Osborne

llvm-svn: 194464
2013-11-12 10:11:26 +00:00
Robert Lytton
d18548882b XCore target: return error for unsupported alignment
llvm-svn: 194463
2013-11-12 10:11:05 +00:00
Wan Xiaofei
b1eca50fd8 Change data structure to memorize computed result in ScalarEvolution
Replace std::map with SmallVector to memorize the cached result since SCEV usually belongs to little Loop/BB
Linear scan on SmallVector is faster than std::map.

Code reviewer : Andrew Trick.
Test result   : Pass Unit Test & LLVM Test Suite

401.bzip2	0.425721	0.419981	101.37%
403.gcc		24.53855	24.2667		101.12%
429.mcf		0.060847	0.059944	101.51%
433.milc	0.646009	0.636119	101.55%
444.namd	1.383928	1.370614	100.97%
445.gobmk	5.836575	5.800225	100.63%
450.soplex	1.911257	1.895963	100.81%
456.hmmer	1.039565	1.032534	100.68%
458.sjeng	0.897401	0.885567	101.34%
464.h264ref	3.645908	3.577991	101.90%
470.lbm		0.049456	0.048398	102.19%
471.omnetpp	5.638575	5.60435		100.61%
bitmnp01	0.045738	0.045291	100.99%
cjpegv2data	0.304359	0.302833	100.50%
idctrn01	0.046433	0.045763	101.46%
quake2		4.534416	4.4952		100.87%
quake		2.688566	2.659208	101.10%
xcsoar		12.42545	12.30385	100.99%
linpack		0.038739	0.03803		101.86%
matrix01	0.053564	0.0528		101.45%
nbench		0.402867	0.395803	101.78%
tblook01	0.021265	0.021015	101.19%
ttsprk01	0.066384	0.065566	101.25%

llvm-svn: 194459
2013-11-12 09:40:41 +00:00
Shuxin Yang
ccc49e9a1b Correct a glitch in r194424 which may invalidate iterator.
llvm-svn: 194457
2013-11-12 08:33:03 +00:00
Matt Arsenault
eebb9d15c4 Add new FileCheck feature to 3.4 release notes
llvm-svn: 194456
2013-11-12 08:05:30 +00:00
Yuchen Wu
c9e944ce3f Revert "Added basic unit test for llvm-cov."
This reverts commit r194451.

Not sure why the tests are failing on the buildbot. They run fine on my
local machine. Could it possibly be because of the endianness of the
architectures? The GCNO and GCDA files are little-endian encoded, and
llvm-cov expects it to remain that way. Is this a safe assumption?

llvm-svn: 194454
2013-11-12 05:57:06 +00:00
Yuchen Wu
12b9b5086e llvm-cov: Added call to update run/program counts.
Also updated test files that were generated from this change.

llvm-svn: 194453
2013-11-12 04:59:08 +00:00
Yuchen Wu
8c734a4736 Added basic unit test for llvm-cov.
This test compares the output of llvm-cov against a coverage file
generated by gcov. Since the source file must be in the current
directory when reading GCNO files, the test will first cd into the
Inputs directory.

llvm-svn: 194451
2013-11-12 04:52:53 +00:00
Matt Arsenault
70be5dff43 R600/SI: Change formatting of printed registers.
Print the range of registers used with a single letter prefix.
This better matches what the shader compiler produces and
is overall less obnoxious than concatenating all of the
subregister names together.

Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1,
it will print s[0:1] and so on.

There doesn't appear to be a straightforward way
to get the actual register info in the InstPrinter,
so this parses the generated name to print with the
new syntax.

The required test changes are pretty nasty, and register
matching regexes are now worse. Since there isn't a way to
add to a variable in FileCheck, some of the tests now don't
check the exact number of registers used, but I don't think that
will be a real problem.

llvm-svn: 194443
2013-11-12 02:35:51 +00:00
Reed Kotler
c6c2273def Change the default branch instruction to be the 16 bit variety for mips16.
This has no material effect at this time since we don't have a direct
object emitter for mips16 and the assembler can't tell them apart. I
place a comment "16 bit inst" for those so that I can tell them apart in the
output. The constant island pass has only been minimally changed to allow
this. More complete branch work is forthcoming but this is the first
step.

llvm-svn: 194442
2013-11-12 02:27:12 +00:00
Reid Kleckner
6703981cf6 Extract a bc attr parsing helper that returns Attribute::None on error
The parsing method still returns llvm::error_code for consistency with
other parsing methods.  Minor cleanup, no functionality change.

llvm-svn: 194437
2013-11-12 01:31:00 +00:00
Matt Arsenault
7970dec395 R600/SI: Add test that fails due to requiring i64 mul for pointers
llvm-svn: 194433
2013-11-11 23:31:02 +00:00
Lang Hames
dcd012fa30 Lower X86::MORESTACK_RET and X86::MORESTACK_RET_RESTORE_R10 in
X86AsmPrinter::EmitInstruction, rather than X86MCInstLower::Lower.

The aim is to improve the reusability of the X86MCInstLower class by making it
more function-like. The X86::MORESTACK_RET_RESTORE_R10 pseudo broke the
function model by emitting an extra instruction to the MCStreamer attached to
the AsmPrinter.

The patch should have no impact on generated code. 
 

llvm-svn: 194431
2013-11-11 23:00:41 +00:00
Andrew Trick
9a4f1fc067 Fix the recently added anyregcc convention to handle spilled operands.
Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!"

The primary purpose of anyregcc is to prevent a patchpoint's call
arguments and return value from being spilled. They must be available
in a register, although the calling convention does not pin the
register. It's up to the front end to avoid using this convention for
calls with more arguments than allocatable registers.

llvm-svn: 194428
2013-11-11 22:40:25 +00:00
Andrew Trick
6abf14ec1a Print new JavaScript calling conventions symbolically.
llvm-svn: 194427
2013-11-11 22:40:22 +00:00
Vincent Lejeune
54d9c8726b R600: Use function inputs to represent data stored in gpr
llvm-svn: 194425
2013-11-11 22:10:24 +00:00
Shuxin Yang
fc370d42f7 Fix PR17952.
The symptom is that an assertion is triggered. The assertion was added by
me to detect the situation when value is propagated from dead blocks.
(We can certainly get rid of assertion; it is safe to do so, because propagating
 value from dead block to alive join node is certainly ok.)

  The root cause of this bug is : edge-splitting is conducted on the fly,
the edge being split could be a dead edge, therefore the block that 
split the critial edge needs to be flagged "dead" as well.

  There are 3 ways to fix this bug:
  1) Get rid of the assertion as I mentioned eariler 
  2) When an dead edge is split, flag the inserted block "dead".
  3) proactively split the critical edges connecting dead and live blocks when
     new dead blocks are revealed.

  This fix go for 3) with additional 2 LOC.

  Testing case was added by Rafael the other day.

llvm-svn: 194424
2013-11-11 22:00:23 +00:00
Akira Hatanaka
3e34a7bec2 [mips] Partially revert r193641. Stack alignment should not be determined by
the floating point register mode.
 

llvm-svn: 194423
2013-11-11 21:49:03 +00:00
Simon Atanasyan
620a19c0b4 Add support for DT_VERxxx and DT_MIPS_xxx .dynamic section entries to the
llvm-readobj.

The patch reviewed by Michael Spencer.
http://llvm-reviews.chandlerc.com/D2113

llvm-svn: 194421
2013-11-11 20:51:48 +00:00
Bob Wilson
f240040c9b Change libLTO back to linking with @executable_path instead of @rpath.
This partially reverts r187641 until ld64 adopts a change to link with an
rpath setting.

llvm-svn: 194418
2013-11-11 20:08:24 +00:00
Arnaud A. de Grandmaison
26d846f560 CalcSpillWeights: allow overidding the spill weight normalizing function
This will enable the PBQP register allocator to provide its own normalizing function.

No functionnal change.

llvm-svn: 194417
2013-11-11 19:56:14 +00:00
Artyom Skrobov
7871752687 [ARM] Add support for MVFR2 which is new in ARMv8
llvm-svn: 194416
2013-11-11 19:56:13 +00:00
Andrew Kaylor
f2093d976d Fixing a problem with iterator validity in RuntimeDyldImpl::resolveExternalSymbols
llvm-svn: 194415
2013-11-11 19:55:10 +00:00
Justin Holewinski
a0efbf3a7e [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment of function parameters
llvm-svn: 194410
2013-11-11 19:28:19 +00:00
Justin Holewinski
0d1f2863f9 [NVPTX] Fix logic error in loading vector parameters of more than 4 components
llvm-svn: 194409
2013-11-11 19:28:16 +00:00
Chad Rosier
8d7ebe36dd [AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194406
2013-11-11 19:11:11 +00:00
Arnaud A. de Grandmaison
8c40e45072 CalcSpillWeights: give a better describing name to calculateSpillWeights
Besides, this relates it more obviously to the VirtRegAuxInfo::calculateSpillWeightAndHint.

No functionnal change.

llvm-svn: 194404
2013-11-11 19:04:45 +00:00
Eric Christopher
67515d7632 Unify the adding of enumerators with the construction of the enumeration.
llvm-svn: 194401
2013-11-11 18:52:39 +00:00
Eric Christopher
bbbbc2a7b7 Formatting.
llvm-svn: 194400
2013-11-11 18:52:36 +00:00
Eric Christopher
0f783ef1e2 80-col.
llvm-svn: 194399
2013-11-11 18:52:33 +00:00
Eric Christopher
97c343d817 Just pass the DIComposite type by value instead of by pointer.
llvm-svn: 194398
2013-11-11 18:52:31 +00:00
Chad Rosier
4848250116 [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
llvm-svn: 194394
2013-11-11 18:04:07 +00:00
Daniel Sanders
a3d78a0bb1 Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too
Reviewers: dsanders

Reviewed By: dsanders

CC: llvm-commits, nadav

Differential Revision: http://llvm-reviews.chandlerc.com/D1958

llvm-svn: 194393
2013-11-11 17:23:41 +00:00
Matheus Almeida
568c6ffeab [mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.
No functional changes.

llvm-svn: 194391
2013-11-11 16:46:20 +00:00
Matheus Almeida
c62765e970 [mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test.
No functional changes.

llvm-svn: 194390
2013-11-11 16:38:55 +00:00
Matheus Almeida
a747f4d24f [mips][msa] CHECK-DAG-ize MSA 2rf_float_int.ll test.
No functional changes.

llvm-svn: 194389
2013-11-11 16:31:46 +00:00
Renato Golin
ed3b88828a Move debug message in vectorizer
No functional change, just better reporting.

llvm-svn: 194388
2013-11-11 16:27:35 +00:00
Matheus Almeida
c1afcbf128 [mips][msa] CHECK-DAG-ize MSA 2rf.ll test.
No functional changes.

llvm-svn: 194387
2013-11-11 16:24:53 +00:00
Matheus Almeida
7ff082f91c [mips][msa] CHECK-DAG-ize MSA 2r.ll test.
No functional changes.

llvm-svn: 194386
2013-11-11 16:16:53 +00:00
Rafael Espindola
a60eb6af02 Add a testcase for pr17852.
llvm-svn: 194385
2013-11-11 15:37:52 +00:00
Hal Finkel
2d9d341e70 Add PPC option for full register names in asm
On non-Darwin PPC systems, we currently strip off the register name prefix
prior to instruction printing. So instead of something like this:

  mr r3, r4

we print this:

  mr 3, 4

The first form is the default on Darwin, and is understood by binutils, but not
yet understood by our integrated assembler. Once our integrated-as understands
full register names as well, this temporary option will be replaced by tying
this functionality to the verbose-asm option. The numeric-only form is
compatible with legacy assemblers and tools, and is also gcc's default on most
PPC systems. On the other hand, it is harder to read, and there are some
analysis tools that expect full register names.

llvm-svn: 194384
2013-11-11 14:58:40 +00:00
Benjamin Kramer
b47354d912 Simplify code. No functionality change.
llvm-svn: 194383
2013-11-11 14:54:34 +00:00
Peter Zotov
83f140c801 [OCaml] Add missing Llvm_target functions
llvm-svn: 194382
2013-11-11 14:47:28 +00:00