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15309 Commits

Author SHA1 Message Date
Chris Lattner
726aae87ee apparently jmpl $1,$2 is an alias for ljmpl, similiarly 
for call.  Add this.

llvm-svn: 113948
 2010-09-15 05:25:21 +00:00
Chris Lattner
5b8a3129a5 Disambiguate lcall/ljmp to the 32-bit version. This happens 
even in 64-bit mode apparently.

llvm-svn: 113945
 2010-09-15 05:14:54 +00:00
Chris Lattner
e542e3e2ad fix the encoding of sldt GR16 to have the 0x66 prefix, and 
add sldt GR32, which isn't documented in the intel manual
but which gas accepts.  Part of rdar://8418316

llvm-svn: 113938
 2010-09-15 04:45:10 +00:00
Chris Lattner
c4a2e044f3 implement aliases for shld/shrd, part of rdar://8418316 
llvm-svn: 113937
 2010-09-15 04:37:18 +00:00
Chris Lattner
ad73a2623c fix rdar://8431880 - rcl/rcr with no shift amount not recognized 
llvm-svn: 113936
 2010-09-15 04:33:27 +00:00
Chris Lattner
c48bd41698 add various broken forms of fnstsw. I didn't add the %rax 
version because it adds a prefix and makes even less sense
than the other broken forms.  This wraps up rdar://8431422

llvm-svn: 113932
 2010-09-15 04:15:16 +00:00
Chris Lattner
b6167a8674 add some aliases for f[u]comi, part of rdar://8431422 
llvm-svn: 113930
 2010-09-15 04:08:38 +00:00
Chris Lattner
c9f1a5cd94 add a bunch of aliases for fp operations with no operand, 
rdar://8431422

llvm-svn: 113929
 2010-09-15 04:04:33 +00:00
Chris Lattner
a9a15c74b1 Diagnose invalid instructions like "incl" with "too few operands for instruction" 
instead of crashing.  This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present

llvm-svn: 113921
 2010-09-15 03:50:11 +00:00
Bob Wilson
9d68270b2e Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and 
storeRegToStackSlot.

llvm-svn: 113918
 2010-09-15 01:48:05 +00:00
Jim Grosbach
050a857211 trailing whitespace 
llvm-svn: 113915
 2010-09-15 01:01:45 +00:00
Dale Johannesen
c7739ca945 Add x86MMX a few more places. 
llvm-svn: 113914
 2010-09-15 00:52:23 +00:00
Jim Grosbach
901a646188 Reapply r113875 with additional cleanups. 
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."

Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.

llvm-svn: 113903
 2010-09-14 23:54:06 +00:00
Chris Lattner
cd4eadce11 add a terrible hack to allow out with dx is parens, a gas bug. 
This fixes PR8114

llvm-svn: 113894
 2010-09-14 23:34:29 +00:00
Eric Christopher
c6075a71ad Emit libcalls for SDIV, this requires some call infrastructure 
that needs to be shared a bit more widely around.

llvm-svn: 113886
 2010-09-14 23:03:37 +00:00
Jim Grosbach
d7e8d8c018 revert 113875 momentarilly. Need to fix the MC disassembler to handle the 
change.

llvm-svn: 113878
 2010-09-14 22:38:39 +00:00
Jim Grosbach
12d12f92ff trailing whitespace cleanup 
llvm-svn: 113877
 2010-09-14 22:27:15 +00:00
Gabor Greif
8856ba094b an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line 
llvm-svn: 113876
 2010-09-14 22:25:16 +00:00
Jim Grosbach
d338306232 The register specified for a dregpair is the corresponding Q register, so to 
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).

llvm-svn: 113875
 2010-09-14 22:20:33 +00:00
Gabor Greif
a9a9743d0d set isCompare for another three Thumb1 instructions 
llvm-svn: 113867
 2010-09-14 22:00:50 +00:00
Jim Grosbach
a43d109cb3 Add predicate and 's' bit operands to PICADD instruction lowering. 
llvm-svn: 113860
 2010-09-14 21:28:17 +00:00
Bob Wilson
fcca92b837 Avoid warnings. 
llvm-svn: 113857
 2010-09-14 21:12:05 +00:00
Jim Grosbach
6ade4ae68d fix comment typo 
llvm-svn: 113856
 2010-09-14 21:05:34 +00:00
Bob Wilson
1a69820d6d Make NEON ld/st pseudo instruction classes take the instruction itinerary as 
an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4).  Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.

llvm-svn: 113854
 2010-09-14 20:59:49 +00:00
Gabor Greif
32fefaf320 set comparable for a bunch of Thumb instructions 
llvm-svn: 113849
 2010-09-14 20:47:43 +00:00
Jim Grosbach
caaab2a7af Don't ignore the CPSR implicit def when lowering a MachineInstruction to an MCInst. 
llvm-svn: 113847
 2010-09-14 20:41:27 +00:00
Jim Grosbach
c04a3f0ae5 Clarify comment 
llvm-svn: 113846
 2010-09-14 20:35:46 +00:00
Gabor Greif
357e2fe748 Eliminate a 'tst' that immediately follows an 'and' 
by morphing the 'and' to its recording form 'andS'.

This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.

I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.

llvm-svn: 113839
 2010-09-14 09:23:22 +00:00
Eric Christopher
3d2aa0da5f Fix QOpcode assignment to Opc. 
llvm-svn: 113837
 2010-09-14 08:31:25 +00:00
Michael J. Spencer
26fe225080 CBackend: Fix MSVC build. 
This may produce warnings on MSVS, but it's better than failures.

llvm-svn: 113834
 2010-09-14 04:27:38 +00:00
Michael J. Spencer
a845c8d2ff CBackend: Cleanup whitespace before I do this next commit. 
llvm-svn: 113833
 2010-09-14 04:27:26 +00:00
Michael J. Spencer
90f807fda5 Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally." 
This reverts commit r113632

Conflicts:

	cmake/modules/AddLLVM.cmake

llvm-svn: 113819
 2010-09-13 23:59:48 +00:00
Bob Wilson
ba02d5b620 Convert some VTBL and VTBX instructions to use pseudo instructions prior to 
register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818
 2010-09-13 23:55:10 +00:00
Bob Wilson
6f35180bec Switch all the NEON vld-lane and vst-lane instructions over to the new 
pseudo-instruction approach.  Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.

llvm-svn: 113812
 2010-09-13 23:01:35 +00:00
Dale Johannesen
eb807a15a3 Fix typos. 128-bit PSHUFB takes 128-bit memory op. 
v8i16 is not an MMX type; put it where it belongs.

llvm-svn: 113785
 2010-09-13 21:15:43 +00:00
Jim Grosbach
a02bbe95be trailing whitespace 
llvm-svn: 113768
 2010-09-13 18:25:42 +00:00
John Thompson
ae3a86d6de Added skeleton for inline asm multiple alternative constraint support. 
llvm-svn: 113766
 2010-09-13 18:15:37 +00:00
Michael J. Spencer
29dfbc4fbb CMake: Fix MSVS build. Although I don't know why this didn't break other build systems... 
This problem is unrelated to the recent dependency tracking change. It
seems like noone noticed the problem because I don't think anyone compiles
any target other than X86 on windows.

llvm-svn: 113727
 2010-09-12 18:32:57 +00:00
Michael J. Spencer
8025489df4 CMake: Fix mingw32 build. 
llvm-svn: 113712
 2010-09-12 03:47:31 +00:00
Chris Lattner
46844daf49 add a missed cmov alias, part of rdar://8416805 
llvm-svn: 113693
 2010-09-11 17:08:22 +00:00
Chris Lattner
57c170e15b add support for all the setCC aliases. Part of rdar://8416805 
llvm-svn: 113692
 2010-09-11 17:06:05 +00:00
Chris Lattner
7cb9d276e0 add support for pushfd/popfd which are aliases for pushfl/popfl. 
This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors

llvm-svn: 113690
 2010-09-11 16:39:16 +00:00
Chris Lattner
1fd69dd039 implement rdar://8407928 - support for in/out with a missing "a" register. 
llvm-svn: 113689
 2010-09-11 16:32:12 +00:00
Chris Lattner
ffe1efe7ef fix the asmparser so that the target is responsible for skipping to 
the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors.  Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:

  foo %eax
  bar %al

This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors

llvm-svn: 113688
 2010-09-11 16:18:25 +00:00
Bill Wendling
038bcd275f Rename ConvertToSetZeroFlag to something more general. 
llvm-svn: 113670
 2010-09-11 00:13:50 +00:00
Bill Wendling
f2b0c99610 No need to recompute the SrcReg and CmpValue. 
llvm-svn: 113666
 2010-09-10 23:46:12 +00:00
Bill Wendling
e54ebc2cbe Move some of the decision logic for converting an instruction into one that sets 
the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.

llvm-svn: 113665
 2010-09-10 23:34:19 +00:00
Eric Christopher
01d361f9ed Start sketching out ARM fast-isel calls. 
llvm-svn: 113662
 2010-09-10 23:18:12 +00:00
Eric Christopher
1364e542aa For consistency. 
llvm-svn: 113659
 2010-09-10 23:10:30 +00:00
Eric Christopher
4bfc1207f1 Newline at end of file. 
llvm-svn: 113654
 2010-09-10 22:46:03 +00:00