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3467 Commits

Author SHA1 Message Date
Nate Begeman
326b3809f4 Whoops, fix a thinko. All cases except SETNE are now handled by the 
target independent code in SelectionDAG.cpp

llvm-svn: 23002
 2005-08-24 05:06:48 +00:00
Nate Begeman
8e1c08e083 Remove unused statistic 
Prefer 'neg X' to 'subfic 0, X' since neg does not set XER[CA]

llvm-svn: 23001
 2005-08-24 05:03:20 +00:00
Nate Begeman
5d3e28b04c Add the "ppc specific" setcc-equivalent select_cc cases 
Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA]

llvm-svn: 23000
 2005-08-24 04:59:21 +00:00
Chris Lattner
f034da3bd4 Add callseq_begin/end support 
Call stil not supported yet

llvm-svn: 22998
 2005-08-24 00:47:15 +00:00
Chris Lattner
0444d66753 Adjust to new livevars interface 
llvm-svn: 22991
 2005-08-23 23:41:14 +00:00
Chris Lattner
51bad854a7 Simplify this code by using LiveVariables::KillsRegister 
llvm-svn: 22988
 2005-08-23 22:49:55 +00:00
Chris Lattner
aba58bd49b Fix PR618 and Regression/CodeGen/CBackend/2005-08-23-Fmod.ll by not emitting 
x%y for 'rem' on fp values.

llvm-svn: 22984
 2005-08-23 20:22:50 +00:00
Chris Lattner
86a4a4745c add a note 
llvm-svn: 22982
 2005-08-23 06:27:59 +00:00
Nate Begeman
a8ec868347 Ack, typo 
llvm-svn: 22981
 2005-08-23 05:45:10 +00:00
Nate Begeman
0ac8bb2fe1 Add an option to make SetCC illegal as a beta option 
llvm-svn: 22979
 2005-08-23 05:42:36 +00:00
Nate Begeman
383c7553a6 Remove some instructions we no longer generate 
llvm-svn: 22976
 2005-08-23 01:16:46 +00:00
Chris Lattner
86ab578e3e Remove some regs that are not used. 
llvm-svn: 22975
 2005-08-22 22:32:13 +00:00
Chris Lattner
362eff4ccd Nate noticed that 30% of the malloc/frees in llc come from calls to LowercaseString 
in the asmprinter.  This changes the .td files to use lower case register names,
avoiding the need to do this call.  This speeds up the asmprinter from 1.52s
to 1.06s on kc++ in a release build.

llvm-svn: 22974
 2005-08-22 22:00:02 +00:00
Chris Lattner
ef8f06856f Fix a crash I introduced into the IA64 backend with my copyfromreg change. 
It used to crash on any function that took float arguments.

llvm-svn: 22973
 2005-08-22 21:33:11 +00:00
Chris Lattner
36b8efcedd Add a pass name for -time-passes output 
llvm-svn: 22970
 2005-08-22 18:28:09 +00:00
Chris Lattner
4c9d1715ff Implement stores. 
llvm-svn: 22963
 2005-08-22 01:27:59 +00:00
Chris Lattner
86aceaf749 Fix compilation of: 
float %test2(float* %P) {
        %Q = load float* %P
        %R = add float %Q, %Q
        ret float %R
}

By returning the right result.

llvm-svn: 22961
 2005-08-22 00:59:14 +00:00
Chris Lattner
81cde8c7b6 Make sure expressions only have one use before emitting them into a place that is conditionally executed 
llvm-svn: 22960
 2005-08-22 00:47:28 +00:00
Chris Lattner
a3f9415a81 Implement most of load support. There is still a bug though. 
llvm-svn: 22959
 2005-08-21 22:31:09 +00:00
Chris Lattner
0d32366da7 Don't print out the MBB label for the entry mbb 
llvm-svn: 22953
 2005-08-21 19:09:33 +00:00
Chris Lattner
d8b7b492fe Simplify the logic for BRTWOWAY_CC handling. The isel code already 
simplifies BRTWOWAY into BR if one of the results is a fall-through.
Unless I'm missing something, there is no reason to duplicate this
in the target-specific code.

llvm-svn: 22952
 2005-08-21 19:03:28 +00:00
Chris Lattner
0f148968ba Implement selection for branches. 
llvm-svn: 22951
 2005-08-21 18:50:37 +00:00
Chris Lattner
1994775d9d If the false value for a select_cc is really simple (has no inputs), evaluate 
it in the block.  This codegens:

int %test(bool %c) {
        %retval = select bool %c, int 17, int 1
        ret int %retval
}

as:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r2, 17
        cmpwi cr0, r3, 0
        bne .LBB_test_2 ;
.LBB_test_1:    ;
        li r2, 1
.LBB_test_2:    ;
        or r3, r2, r2
        blr

instead of:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r2, 17
        li r4, 1
        cmpwi cr0, r3, 0
        bne .LBB_test_2 ;
.LBB_test_1:    ;
        or r2, r4, r4
.LBB_test_2:    ;
        or r3, r2, r2
        blr

... which is one fewer instruction.  The savings are more significant for
global address and constantfp nodes.

llvm-svn: 22946
 2005-08-21 17:41:11 +00:00
Duraid Madina
06affa0edd reenable collapse of loadimm+AND -> dep.z (thanks guys) 
llvm-svn: 22944
 2005-08-21 15:43:53 +00:00
Jim Laskey
43192e173f Repair an out by one error for IA64. 
llvm-svn: 22942
 2005-08-20 11:05:23 +00:00
Chris Lattner
9fbbc41021 add support for global address, including PIC support. 
This REALLY should be lowered by the legalizer!

llvm-svn: 22941
 2005-08-19 22:38:53 +00:00
Chris Lattner
a8f147c1b4 Fix a typeo, no wonder all tokenfactor edges were the same! 
llvm-svn: 22935
 2005-08-19 21:33:02 +00:00
Chris Lattner
2ac3fd08d2 Split RegisterClass 'Methods' into MethodProtos and MethodBodies 
llvm-svn: 22929
 2005-08-19 19:13:20 +00:00
Chris Lattner
78107cb342 put reg classes into namespace 
llvm-svn: 22927
 2005-08-19 18:53:43 +00:00
Chris Lattner
2b1d327d29 Put reg classes into namespaces 
llvm-svn: 22926
 2005-08-19 18:52:55 +00:00
Chris Lattner
f86654ffde Put register classes into namespaces 
llvm-svn: 22925
 2005-08-19 18:51:57 +00:00
Chris Lattner
9d61d4a3e4 Put register classes in namespaces 
llvm-svn: 22924
 2005-08-19 18:50:46 +00:00
Chris Lattner
15d2e8a253 Fix code that assumes the register info will be dumped into a target 
namespace instead of the reg class namespace.  Update getRegClassForType()
to use modified names due to tblgen change.

llvm-svn: 22923
 2005-08-19 18:50:11 +00:00
Chris Lattner
47005fe346 put reg classes in namespaces 
llvm-svn: 22922
 2005-08-19 18:49:22 +00:00
Chris Lattner
9a9fe27bd2 Require that targets specify a namespace for their register classes. 
llvm-svn: 22921
 2005-08-19 18:48:48 +00:00
Chris Lattner
61526c0f6c The skeleton target has never had an isel 
llvm-svn: 22917
 2005-08-19 18:35:41 +00:00
Chris Lattner
f0b42a6f29 This code has always been dead on itanium 
llvm-svn: 22916
 2005-08-19 18:34:37 +00:00
Chris Lattner
b46e525e23 This code has always been dead for alpha 
llvm-svn: 22915
 2005-08-19 18:33:26 +00:00
Chris Lattner
e894de1791 The simple isel being gone makes this dead! 
llvm-svn: 22914
 2005-08-19 18:32:03 +00:00
Chris Lattner
f0e731ea49 Now that the simple isels are dead, so is this. 
llvm-svn: 22913
 2005-08-19 18:30:39 +00:00
Chris Lattner
db827889e3 Sparcv9 gets no operand info 
llvm-svn: 22909
 2005-08-19 16:56:56 +00:00
Duraid Madina
4efc0b6f2b a bugfix (up top) and a quick repair job: disable generation of dep.z 
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.

llvm-svn: 22904
 2005-08-19 13:25:50 +00:00
Nate Begeman
88bfe8a7c3 Fix a bug where we were passing the wrong number of arguments to an 
instruction.

llvm-svn: 22901
 2005-08-19 03:42:28 +00:00
Chris Lattner
5cfc567fb8 mark variable arity instructions as such. Alpha wins the battle for 
cleanest backend in this metric :)

llvm-svn: 22893
 2005-08-19 00:51:37 +00:00
Chris Lattner
5194ff37c4 Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR. 
I'm not convinced this is all of them,  but I can't do much testing, because
IA64 LLC crashes on big programs :(

llvm-svn: 22892
 2005-08-19 00:47:42 +00:00
Chris Lattner
d7bd59d77e add a few missing cases 
llvm-svn: 22891
 2005-08-19 00:41:29 +00:00
Chris Lattner
f62a66a21c Give ADJCALLSTACKDOWN/UP the correct operands. 
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.

llvm-svn: 22890
 2005-08-19 00:38:22 +00:00
Nate Begeman
1182e06dcf ISD::OR, and it's accompanying SelectBitfieldInsert 
llvm-svn: 22889
 2005-08-19 00:38:14 +00:00
Chris Lattner
abad70eaf8 The variable SAR's only take one operand too 
llvm-svn: 22888
 2005-08-19 00:31:37 +00:00
Chris Lattner
8ce7dd449a Stop adding bogus operands to variable shifts on X86. These instructions 
only take one operand.  The other comes implicitly in through CL.

llvm-svn: 22887
 2005-08-19 00:16:17 +00:00