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100 Commits

Author SHA1 Message Date
Eric Christopher
0e238efc7d Rewrite aesimc handling. It only takes a single input and has a single 
dest.

llvm-svn: 100252
 2010-04-02 23:48:33 +00:00
Eric Christopher
7263b3d802 Fix typo aeskeygenassist -> aeskeygenassist128. 
llvm-svn: 100250
 2010-04-02 23:29:36 +00:00
Eric Christopher
f6603c89d3 Add aeskeygenassist intrinsic and rename all of the aes intrinsics to 
aes instead of sse4.2.  Add a brief todo for a subtarget flag and rework
the aeskeygenassist instruction to more closely match the docs.

llvm-svn: 100078
 2010-04-01 03:05:45 +00:00
Eric Christopher
4c3a3208e3 Remove the pmulld intrinsic and autoupdate it as a vector multiply. 
Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.

llvm-svn: 99910
 2010-03-30 18:49:01 +00:00
Bob Wilson
04e9ff15cb Reapply Kevin's change 94440, now that Chris has fixed the limitation on 
opcode values fitting in one byte (svn r99494).

llvm-svn: 99514
 2010-03-25 16:36:14 +00:00
Bob Wilson
d5673d9f1f Speculatively revert this to see if it fixes buildbot failures. 
--- Reverse-merging r99440 into '.':
U    test/MC/AsmParser/X86/x86_32-bit_cat.s
U    test/MC/AsmParser/X86/x86_32-encoding.s
U    include/llvm/IntrinsicsX86.td
U    include/llvm/CodeGen/SelectionDAGNodes.h
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 99450
 2010-03-24 23:26:29 +00:00
Kevin Enderby
9cab7fdb12 Added the Advanced Encryption Standard (AES) Instructions. 
llvm-svn: 99440
 2010-03-24 22:33:33 +00:00
Chris Lattner
4eac41e12e [llvm_void_ty] is no longer needed for result types, 
just use an empty result list.

llvm-svn: 99346
 2010-03-23 23:46:07 +00:00
Kevin Enderby
766909ae3b Fixed the encoding problems of the crc32 instructions. All had the Operand size 
override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.

llvm-svn: 98980
 2010-03-19 20:04:42 +00:00
David Greene
c3f9f7a3db Revert r92939. These intrinsics get matched to LLVM instructions, 
so removing at Chris' request.

llvm-svn: 92947
 2010-01-07 21:43:58 +00:00
David Greene
7c9c709d3d Add some "missing" instrinsics to make the SSE intrinsic set a bit more 
orthogonal.

llvm-svn: 92939
 2010-01-07 19:47:43 +00:00
Eric Christopher
8a948265a1 Remove the gcc builtins from the intrinsics, we'll lower them 
explicitly so we can check arguments.

llvm-svn: 90199
 2009-12-01 03:18:26 +00:00
Sean Callanan
78ee7f5d57 Recommitting PALIGNR shift width fixes. 
Thanks to Daniel Dunbar for fixing clang intrinsics:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=89499

llvm-svn: 89500
 2009-11-20 22:28:42 +00:00
Sean Callanan
d92626fc0d Reverting PALIGNR fix until I figure out how this 
broke the Clang testsuite.

llvm-svn: 89495
 2009-11-20 22:09:28 +00:00
Sean Callanan
0da77167d3 Fixed PALIGNR to take 8-bit rotations in all cases. 
Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).

llvm-svn: 89491
 2009-11-20 21:40:28 +00:00
Eric Christopher
593cfc9984 Fix PR5315, original patch by Nicolas Capens! 
llvm-svn: 86203
 2009-11-06 00:11:57 +00:00
Eric Christopher
6fd0214a67 Add sse4.2 string/text processing intrinsics. We'll select these later. 
llvm-svn: 79037
 2009-08-14 20:27:57 +00:00
Eric Christopher
12c6e08c7c Whitespace cleanup. 
llvm-svn: 79036
 2009-08-14 20:27:12 +00:00
Eric Christopher
93437b0d2e Fix some cut and paste-os. 
llvm-svn: 78493
 2009-08-08 20:09:33 +00:00
Eric Christopher
58b627bed1 Define intrinsics for crc instruction. 
llvm-svn: 78482
 2009-08-08 18:07:59 +00:00
Eric Christopher
c7b97d1f03 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.

llvm-svn: 77407
 2009-07-29 00:28:05 +00:00
Eric Christopher
2c688c183d Remove intrinsic support for __builtin_ia32_vec_set_v16qi and 
__builtin_ia32_vec_set_v4si as these should be lowered in the
front-end to inserts.

llvm-svn: 76714
 2009-07-22 01:11:48 +00:00
Eric Christopher
626e2c87ee Add intrinsic for __builtin_ia32_vec_set_v4si which turns out to be 
pinsrd in sse4.1.

llvm-svn: 76684
 2009-07-21 23:43:14 +00:00
Evan Cheng
4014a9a5b8 ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. 
llvm-svn: 65499
 2009-02-26 03:12:02 +00:00
Bill Wendling
9dc2bd7973 Modify the intrinsics pattern to separate out the "return" types from the 
"parameter" types. An intrinsic can now return a multiple return values like
this:

  def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty],
                                    [LLVMMatchType<0>, LLVMMatchType<0>]>;

llvm-svn: 59237
 2008-11-13 09:08:33 +00:00
Mon P Wang
98c2e01394 Removed pinsrd and pinsrq intrinsics because the code generator does not support 
them since they map to insert element

llvm-svn: 57564
 2008-10-15 06:27:16 +00:00
Dale Johannesen
03d0a7d70c Fix SSE4.1 roundss, roundsd. While the instructions have 
the same pattern as roundpd/roundps, the Intel compiler 
builtins do not:  rounds* has an extra operand.  Fixes
gcc.target/i386/sse4_1-rounds[sd]-[1234].c

llvm-svn: 57370
 2008-10-10 23:51:03 +00:00
Bill Wendling
1c97db4090 "The original bug was a complaint that _mm_srli_si128 mis-compiled when passed 
a constant vector ("{0x123, 0x456}" syntax).  The fix is to simplify the
_mm_srli_si128 macro, and  move the "* 8" from the macro into the compiler
back-end.  I can't change the existing __builtins because so many people are
using them :-(."
Patch by Stuart Hastings!

llvm-svn: 56944
 2008-10-02 05:56:52 +00:00
Nate Begeman
af01bfff99 SSE codegen for vsetcc nodes 
llvm-svn: 53719
 2008-07-17 16:51:19 +00:00
Evan Cheng
4e7b7b21a2 Horizontal-add instructions are not commutative. 
llvm-svn: 52363
 2008-06-16 21:16:24 +00:00
Evan Cheng
d27948e716 - Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. 
- Mark lots of X86 intrinsics as "Commutative" to allow load folding.

llvm-svn: 52353
 2008-06-16 20:29:38 +00:00
Evan Cheng
e5e0b4660d Eliminate x86.sse2.punpckh.qdq and x86.sse2.punpckl.qdq. 
llvm-svn: 51533
 2008-05-24 02:56:30 +00:00
Evan Cheng
564238c841 Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and x86.sse2.unpckl.pd intrinsics. These will be lowered into shuffles. 
llvm-svn: 51531
 2008-05-24 02:14:05 +00:00
Evan Cheng
47bd4b07a8 Remove x86.sse2.loadh.pd and x86.sse2.loadl.pd. These will be lowered into load and shuffle instructions. 
llvm-svn: 51521
 2008-05-24 00:07:06 +00:00
Evan Cheng
c1c2adbfc6 Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. 
llvm-svn: 50601
 2008-05-03 00:52:09 +00:00
Evan Cheng
4ae9fee64c Undo 48570. Correctly match mmx shift instructions with an immediate operand. 
llvm-svn: 48627
 2008-03-21 00:40:09 +00:00
Evan Cheng
6f729b2820 Add intrinsics to match mmx shift builtin's with immediate operand. 
llvm-svn: 48569
 2008-03-19 23:38:52 +00:00
Nate Begeman
f50ef51ded __builtin_ia32_movntdqa reads memory 
llvm-svn: 48431
 2008-03-16 21:15:47 +00:00
Dale Johannesen
bf7691e2e8 Missed one. 
llvm-svn: 46733
 2008-02-05 01:12:10 +00:00
Dale Johannesen
9b7f4064e3 Do not unconditionally redefine vec_ext_v16qi and 
vec_ext_v4si builtins.  This is a hack; they should
be defined here, then resolved in the X86 BE.
However there is enough other stuff missing in the
X86 BE for SSE41 that this will do for now.

llvm-svn: 46727
 2008-02-04 23:27:29 +00:00
Nate Begeman
ead8dfeef2 SSE 4.1 Intrinsics and detection 
llvm-svn: 46681
 2008-02-03 07:18:54 +00:00
Evan Cheng
f91cfb435f Fix sse2.psrl.w and sse2.psrl.q definitions. 
llvm-svn: 45772
 2008-01-09 02:16:44 +00:00
Chris Lattner
7a9b0bf0eb remove attribution from a variety of miscellaneous files. 
llvm-svn: 45425
 2007-12-29 22:59:10 +00:00
Evan Cheng
ec3c87a7ef Add a few more missing gcc builtin's. 
llvm-svn: 45278
 2007-12-21 01:30:39 +00:00
Evan Cheng
efdab94d4a Type specification didn't match gcc's. 
llvm-svn: 45260
 2007-12-20 09:35:28 +00:00
Evan Cheng
8b4947fe98 Remove int_x86_sse2_movl_dq. It's replaced with a string compare. 
llvm-svn: 45140
 2007-12-18 01:04:25 +00:00
Evan Cheng
21f2afd4df These have matching builtin's in 4.2. 
llvm-svn: 45139
 2007-12-18 00:52:20 +00:00
Evan Cheng
d9df071ead Bring back int_x86_sse2_movl_dq intrinsic for backward compatibility. Make sure 
it's auto-upgraded to a shufflevector instruction.

llvm-svn: 45131
 2007-12-17 22:33:23 +00:00
Evan Cheng
063e019ff6 __builtin_ia32_movqv4si is now expanded to a shuffle. 
llvm-svn: 45057
 2007-12-15 02:54:12 +00:00
Anders Carlsson
900a684ae7 All MMX shift instructions took a <2 x i32> vector as the shift amount parameter. Change this to be <1 x i64> instead, which matches the assembler instruction. 
llvm-svn: 45027
 2007-12-14 06:38:54 +00:00