RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 16:33:37 +01:00
Code Issues Projects Releases Wiki Activity
79,021 Commits 4 Branches 5 Tags 704 MiB
7425820374
Commit Graph

79021 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Kostya Serebryany
c78b00cab4 [asan] add a test for instrumenting globals 
llvm-svn: 146718
 2011-12-16 01:28:19 +00:00
Jim Grosbach
42bf8d8526 ARM NEON aliases for vmovq.f* 
llvm-svn: 146714
 2011-12-16 00:12:22 +00:00
Jakob Stoklund Olesen
f51f7724cb Extract a method. No functional change. 
llvm-svn: 146713
 2011-12-16 00:12:05 +00:00
Daniel Dunbar
68de82c003 llvm-config: Fix --targets-built, I changed this to use the registry but wasn't 
properly initializing the target infos. I decided it wasn't worth linking them
in for this, so just switched back to using the Makefile variable for now. We
can reconsider later if we ever get pluggable targets.

llvm-svn: 146711
 2011-12-16 00:04:43 +00:00
Jim Grosbach
5f14a4c5d4 Thumb2 ADR assembly parsing w/o the .w suffix. 
llvm-svn: 146710
 2011-12-15 23:52:17 +00:00
Eli Friedman
f626b19bda Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
llvm-svn: 146709
 2011-12-15 23:46:18 +00:00
Daniel Dunbar
f961e224ec llvm-config: Update help text for removal of "backend" pseudo component. 
llvm-svn: 146708
 2011-12-15 23:43:17 +00:00
Daniel Dunbar
d2627d2855 build/unittests: Fix llvm-config names for gtest libraries, and bring Makefile 
library names in line with those used by CMake.
 - Patch by Johannes Obermayr, with tweaks by me.

llvm-svn: 146706
 2011-12-15 23:35:08 +00:00
Nick Lewycky
88e64bacfa Move parts of lib/Target that use CodeGen into lib/CodeGen. 
llvm-svn: 146702
 2011-12-15 22:58:58 +00:00
Eli Friedman
7e3cbd0db2 Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) 
llvm-svn: 146700
 2011-12-15 22:56:53 +00:00
Jim Grosbach
30f4b285a6 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Kostya Serebryany
847d2d2c25 [asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports. 
llvm-svn: 146698
 2011-12-15 22:55:55 +00:00
Tony Linthicum
31c6f9b096 Add MCTargetDesc library to Hexagon target 
llvm-svn: 146692
 2011-12-15 22:29:08 +00:00
Jim Grosbach
b79d2a8f50 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Jakob Stoklund Olesen
cd03c93e33 Enable proper constant island alignment by default. 
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690
 2011-12-15 22:14:45 +00:00
Chad Rosier
62ebee9859 Add missing zmovl AVX patterns which were causing crashes. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689
 2011-12-15 22:11:31 +00:00
Kostya Serebryany
65849ee22a [asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part. 
llvm-svn: 146688
 2011-12-15 21:59:03 +00:00
Jim Grosbach
3ee3c6dc3e Silence warning. 
llvm-svn: 146686
 2011-12-15 21:54:55 +00:00
Jim Grosbach
8ed1253ef3 ARM NEON two-register double spaced register list parsing support. 
llvm-svn: 146685
 2011-12-15 21:44:33 +00:00
Chad Rosier
e74b3b1469 Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684
 2011-12-15 21:34:44 +00:00
Eli Friedman
8a99f9655e Zap unnecessary semicolons. 
llvm-svn: 146682
 2011-12-15 21:11:38 +00:00
Lang Hames
d5cee672a7 Set specific target cpu for testcase. 
llvm-svn: 146678
 2011-12-15 20:22:34 +00:00
Lang Hames
0e361e816d Added test case for r146671. 
llvm-svn: 146675
 2011-12-15 19:56:07 +00:00
Jakob Stoklund Olesen
bc821819f3 Use the proper comparator for set_intersection. 
llvm-svn: 146674
 2011-12-15 19:26:23 +00:00
Lang Hames
d86b47a279 Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>. 
llvm-svn: 146671
 2011-12-15 18:57:27 +00:00
Devang Patel
b8b77459d6 Update DebugLoc while merging nodes at -O0. 
Patch by Kyriakos Georgiou!

llvm-svn: 146670
 2011-12-15 18:21:18 +00:00
Hal Finkel
e8220d9927 Add a test case to make sure that the nop really does follow the bl on ppc64 elf 
llvm-svn: 146666
 2011-12-15 17:59:23 +00:00
Devang Patel
9578694f5b Virtual table holder field is either metadata or null. 
llvm-svn: 146665
 2011-12-15 17:55:56 +00:00
Hal Finkel
f480143f08 Ensure that the nop that should follow a bl call in PPC64 ELF actually does 
llvm-svn: 146664
 2011-12-15 17:54:01 +00:00
Jakob Stoklund Olesen
9945c85b52 Synthesize missing register class intersections. 
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B.  This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    tGPR_and_tcGPR
    hGPR_and_tcGPR

X86:
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR64_NOSP_and_GR64_TC
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_TC
    GR32_NOAX_and_GR32_NOSP
    GR64_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_ABCD_and_GR32_NOAX
    GR64_ABCD_and_GR64_TC
    GR32_NOAX_and_GR32_TC
    GR32_AD_and_GR32_NOAX

Other targets are unaffected.

llvm-svn: 146657
 2011-12-15 16:48:55 +00:00
Richard Osborne
5f2d0e64e0 Pass optLevel to XCoreDAGToDAGISel. 
Patch by Kyriakos Georgiou.

llvm-svn: 146656
 2011-12-15 15:18:35 +00:00
Eli Friedman
09abc453ac Fix test. 
llvm-svn: 146642
 2011-12-15 04:52:47 +00:00
Eli Friedman
f6ae3a7caf Make constant folding for GEPs a bit more aggressive. 
llvm-svn: 146639
 2011-12-15 04:33:48 +00:00
Eli Friedman
71c0914b64 Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570. 
llvm-svn: 146630
 2011-12-15 02:07:20 +00:00
Chad Rosier
dcfc5e1dd0 Use SmallVector/assign(), rather than std::vector/push_back(). 
llvm-svn: 146627
 2011-12-15 01:16:09 +00:00
Chad Rosier
b93733686c Add support for lowering fneg when AVX is enabled. 
rdar://10566486

llvm-svn: 146625
 2011-12-15 01:02:25 +00:00
Pete Cooper
550b96ab46 Added InstCombine for "select cond, ~cond, x" type patterns 
These can be reduced to "~cond & x" or "~cond | x"

llvm-svn: 146624
 2011-12-15 00:56:45 +00:00
Owen Anderson
4f7037cb7c Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. These are already marked as illegal by default. 
llvm-svn: 146623
 2011-12-15 00:54:12 +00:00
Eli Friedman
5dd57bb40a Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575. 
llvm-svn: 146621
 2011-12-15 00:50:34 +00:00
Bill Wendling
cb4ed696ef Re-re-enable compact unwind after fixing a failure in SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order. 
llvm-svn: 146617
 2011-12-15 00:14:24 +00:00
Kevin Enderby
c65cec89e5 Another improvement to the implementation of .incbin directive by avoiding a 
buffer copy.  Suggestion by Chris Lattner!

llvm-svn: 146614
 2011-12-15 00:00:27 +00:00
Bill Wendling
e9bd145105 The saved registers weren't being processed in the correct order. This lead to 
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.

llvm-svn: 146612
 2011-12-14 23:53:24 +00:00
Dan Gohman
1add31cc93 Move Instruction::isSafeToSpeculativelyExecute out of VMCore and 
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.

llvm-svn: 146610
 2011-12-14 23:49:11 +00:00
Jakob Stoklund Olesen
215059cb96 Consider CPE alignment in CreateNewWater(). 
An aligned constant pool entry may require extra alignment padding where
the new water is created.  Take that into account when computing offset.

Also consider the alignment of other constant pool entries when
splitting a basic block.  Alignment padding may make it necessary to
move the split point higher.

llvm-svn: 146609
 2011-12-14 23:48:54 +00:00
Jim Grosbach
b09a003fa6 ARM NEON better assembly operand range checking for lane indices of VLD/VST. 
llvm-svn: 146608
 2011-12-14 23:35:06 +00:00
Jim Grosbach
75db252aee ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
llvm-svn: 146605
 2011-12-14 23:25:46 +00:00
Devang Patel
0db1ed1a48 Do not sink instruction, if it is not profitable. 
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.

Radar 10266272.

llvm-svn: 146604
 2011-12-14 23:20:38 +00:00
Evan Cheng
638936d9cb Add a blurb about MachineInstr bundling support. 
llvm-svn: 146603
 2011-12-14 22:57:45 +00:00
Bill Wendling
7fca2377aa Reapply r146481 with a fix to create the Builder value in the correct place and 
with the correct iterator.
<rdar://problem/10530851>

llvm-svn: 146600
 2011-12-14 22:45:33 +00:00
Kevin Enderby
bc6d6388c2 Improve the implementation of .incbin directive by replacing a loop by using 
getStreamer().EmitBytes.  Suggestion by Benjamin Kramer!

llvm-svn: 146599
 2011-12-14 22:34:45 +00:00