Bill Wendling
7cba44defc
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
...
hang, and possibly SPEC/CINT2006/464_h264ref.
llvm-svn: 141560
2011-10-10 18:27:30 +00:00
Bill Wendling
94258753c7
When getting the number of bits necessary for addressing mode
...
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
llvm-svn: 141529
2011-10-10 07:24:23 +00:00
Chad Rosier
2fc181986a
Fix a regression from r138445. If we're loading from the frame/base pointer
...
the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707
llvm-svn: 141523
2011-10-10 01:03:35 +00:00
Anton Korobeynikov
b0534f0113
Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
...
llvm-svn: 141481
2011-10-08 08:38:45 +00:00
Jim Grosbach
94980a23e6
ARM NEON assembly parsing and encoding for VDUP(scalar).
...
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
Jim Grosbach
cb48e1fe60
ARM prefix asmparser operand kind enums for readability.
...
llvm-svn: 141438
2011-10-07 23:24:09 +00:00
Bill Wendling
a95511a253
Take all of the invoke basic blocks and make the dispatch basic block their new
...
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
llvm-svn: 141436
2011-10-07 23:18:02 +00:00
Bill Wendling
1f7c16c63f
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
...
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
llvm-svn: 141419
2011-10-07 22:08:37 +00:00
Bill Wendling
0f5b533c48
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
...
do. This will be useful later on with the new SJLJ stuff.
llvm-svn: 141416
2011-10-07 21:25:38 +00:00
Jim Grosbach
d3c2b772ee
Improve ARM assembly parser diagnostic for unexpected tokens.
...
Consider:
mov r8, r11 fred
Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list
^
Now we generate:
x.s:5:14: error: unexpected token in argument list
mov r8, r11 fred
^
llvm-svn: 141380
2011-10-07 18:27:04 +00:00
Bob Wilson
b55a64ae72
Reenable tail calls for iOS 5.0 and later.
...
llvm-svn: 141370
2011-10-07 17:17:49 +00:00
Bob Wilson
d8856e17fe
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
...
llvm-svn: 141368
2011-10-07 16:59:21 +00:00
Anton Korobeynikov
0944a4c5cc
Peephole optimization for ABS on ARM.
...
Patch by Ana Pazos!
llvm-svn: 141365
2011-10-07 16:15:08 +00:00
Bill Wendling
5492d7a175
Use the correct vreg here.
...
llvm-svn: 141342
2011-10-06 23:41:14 +00:00
Bill Wendling
e34c65724b
Generate the dispatch code for a 'thumb' function. This is very similar to the
...
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.
llvm-svn: 141341
2011-10-06 23:37:36 +00:00
Owen Anderson
dc57f29896
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
...
llvm-svn: 141339
2011-10-06 23:33:11 +00:00
Bill Wendling
82b6f24ee4
Generate the dispatch table for ARM mode.
...
llvm-svn: 141327
2011-10-06 22:53:00 +00:00
Bill Wendling
3c68e1d212
Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
...
llvm-svn: 141323
2011-10-06 22:18:16 +00:00
Bill Wendling
c8c252a859
Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)
...
Place the immediate to OR into a register so that it works.
llvm-svn: 141319
2011-10-06 21:51:21 +00:00
Bill Wendling
e79ca82af3
* Set the low bit of the return address when we are in thumb mode.
...
* Some code cleanup.
llvm-svn: 141317
2011-10-06 21:29:56 +00:00
Peter Collingbourne
253c6a3690
Build system infrastructure for multiple tblgens.
...
llvm-svn: 141266
2011-10-06 01:51:51 +00:00
Bill Wendling
73eb058991
Add the MBBs before inserting the instructions. Doing it afterwards could lead
...
to an infinite loop because of the def-use chains.
Also use a frame load instead of store for the LD instruction.
llvm-svn: 141263
2011-10-06 00:53:33 +00:00
Cameron Zwarich
5fb7c6643e
Always merge profitable shifts on A9, not just when they have a single use.
...
llvm-svn: 141248
2011-10-05 23:39:02 +00:00
Cameron Zwarich
cc5f846d58
Remove a check from ARM shifted operand isel helper methods, which were blocking
...
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
llvm-svn: 141247
2011-10-05 23:38:50 +00:00
Bill Wendling
02aa225b72
Get the proper call site numbers for the landing pads. Also remove a magic
...
number (18) for the proper addressing mode.
llvm-svn: 141245
2011-10-05 23:28:57 +00:00
Owen Anderson
2d1e930b65
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
...
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
Cameron Zwarich
1f890576e3
Add braces around something that throws me for a loop.
...
llvm-svn: 141173
2011-10-05 08:59:10 +00:00
Cameron Zwarich
0cb2071d35
There is no point in setting out-parameters for a ComplexPattern function when
...
it returns false, at least as far as I could tell by reading the code.
llvm-svn: 141172
2011-10-05 08:59:05 +00:00
Bill Wendling
da6fd6f972
Look at the number of entries in the jump table and jump to a 'trap' block if
...
the value exceeds that number.
llvm-svn: 141143
2011-10-05 00:39:32 +00:00
Bill Wendling
db8e0d2dee
Checkpoint for SJLJ EH code.
...
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
llvm-svn: 141140
2011-10-05 00:02:33 +00:00
Owen Anderson
e255773f3d
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
Kevin Enderby
5a09a8db55
Adding back support for printing operands symbolically to ARM's new disassembler
...
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
Jim Grosbach
f38874e79e
ARM assembly parsing and encoding for VMOV immediate.
...
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
Jim Grosbach
5723a6f6ea
Tidy up. 80 columns.
...
llvm-svn: 141043
2011-10-03 23:03:26 +00:00
Bill Wendling
68ee098b5a
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
...
llvm-svn: 141042
2011-10-03 22:44:15 +00:00
Jim Grosbach
c69258c747
ARM parsing/encoding for VCMP/VCMPE.
...
llvm-svn: 141038
2011-10-03 22:30:24 +00:00
Bill Wendling
834bb83a41
Check-pointing the new SjLj EH lowering.
...
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
llvm-svn: 141031
2011-10-03 21:25:38 +00:00
Jim Grosbach
21a9f8f50f
ARM assembly parsing and encoding for VMRS/FMSTAT.
...
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
Jim Grosbach
c7a9669343
Thumb2 ADD/SUB can take SP as a destination register.
...
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
llvm-svn: 141020
2011-10-03 20:51:59 +00:00
Chad Rosier
2cb0d1eddf
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
...
to appease nightly testers. Not quite there yet.
llvm-svn: 140953
2011-10-01 19:30:36 +00:00
Bill Wendling
d6d232142d
No one should be using the method directly. Assert if they do.
...
llvm-svn: 140947
2011-10-01 12:47:34 +00:00
Bill Wendling
3ce912d5b8
Add a convenience method to tell if two things are equal.
...
llvm-svn: 140946
2011-10-01 12:44:28 +00:00
Bill Wendling
a23068ec02
Use the ARMConstantPoolMBB class to handle the MBB values.
...
llvm-svn: 140943
2011-10-01 09:30:42 +00:00
Bill Wendling
a925d1339f
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
...
llvm-svn: 140942
2011-10-01 09:19:10 +00:00
Bill Wendling
aab50632f6
Remove dead code.
...
llvm-svn: 140941
2011-10-01 09:05:12 +00:00
Bill Wendling
0049e4398d
Remove now dead methods and ivar.
...
llvm-svn: 140940
2011-10-01 09:04:18 +00:00
Bill Wendling
c7bf6da86d
Use the new ARMConstantPoolSymbol class to handle external symbols.
...
llvm-svn: 140939
2011-10-01 08:58:29 +00:00
Bill Wendling
4563d806a7
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
...
llvm-svn: 140938
2011-10-01 08:36:59 +00:00
Bill Wendling
67b6d8a185
Remove now dead methods and ivar from ARMConstantPoolValue.
...
llvm-svn: 140937
2011-10-01 08:02:05 +00:00
Bill Wendling
1d585d7961
Switch over to using ARMConstantPoolConstant for global variables, functions,
...
and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
Bill Wendling
9356ee3bd7
Some more refactoring.
...
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
llvm-svn: 140935
2011-10-01 07:52:37 +00:00
Bill Wendling
9ad0742c3f
Add a Create method that accepts 'kind' and 'pcadj' arguments.
...
llvm-svn: 140934
2011-10-01 06:44:24 +00:00
Bill Wendling
33b0c55f4d
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
...
pool value.
It's not used right now, but will be soon.
llvm-svn: 140933
2011-10-01 06:40:33 +00:00
Chad Rosier
ff29430882
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
...
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
llvm-svn: 140924
2011-10-01 02:03:18 +00:00
Jakob Stoklund Olesen
010e9bb778
Store sub-class lists as a bit vector.
...
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
llvm-svn: 140898
2011-09-30 22:19:07 +00:00
Jim Grosbach
355190250f
Correct for my over-eager delete finger.
...
llvm-svn: 140892
2011-09-30 22:02:45 +00:00
Bill Wendling
1485fec8b1
Constify 'isLSDA' and move a method out-of-line.
...
llvm-svn: 140868
2011-09-30 18:42:06 +00:00
Jim Grosbach
44047da675
ARM Darwin default relocation model is PIC.
...
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
Jim Grosbach
5b31ef50f5
ARM Fixup valus for movt/movw are for the whole value.
...
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
llvm-svn: 140861
2011-09-30 17:23:05 +00:00
Jim Grosbach
d94ffffc87
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
Bill Wendling
ee48218f94
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
...
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
Bill Wendling
de36760902
Support creating a constant pool value for a machine basic block.
...
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
NAKAMURA Takumi
f82662e1f6
Target/ARM: Unbreak! CMake! Build!
...
llvm-svn: 140774
2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen
a2a0ba4d56
Delete NEONMoveFix, now unused.
...
llvm-svn: 140773
2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen
cfd5280df5
Use ExecutionDepsFix instead of NEONMoveFix.
...
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
Bill Wendling
cc7e50a465
Move to ISelLowering.
...
llvm-svn: 140754
2011-09-29 01:13:55 +00:00
Evan Cheng
1e53900b70
Tighten a ARM dag combine condition to avoid an identity transformation, which
...
ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
2011-09-28 23:16:31 +00:00
Bill Wendling
2400aacfb7
Perform the lowering only if there are invokes.
...
llvm-svn: 140719
2011-09-28 20:29:45 +00:00
Bill Wendling
37088b0660
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
...
llvm-svn: 140718
2011-09-28 20:29:28 +00:00
James Molloy
c4fcff419c
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
Ted Kremenek
d233d7b066
Unbreak CMake build.
...
llvm-svn: 140655
2011-09-27 23:29:59 +00:00
Jakob Stoklund Olesen
2fc08f4eeb
Implement TII::get/setExecutionDomain() for ARM.
...
llvm-svn: 140653
2011-09-27 22:57:21 +00:00
Jim Grosbach
b503a2183e
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
Bill Wendling
c63b31e1ec
This is the start of the new SjLj EH preparation pass, which will replace the
...
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
2011-09-27 22:14:12 +00:00
Jim Grosbach
e883e939a3
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
...
Naming conventions consistency. No functional change.
llvm-svn: 140636
2011-09-27 20:59:33 +00:00
Jakob Stoklund Olesen
08b5751146
Use existing function.
...
llvm-svn: 140615
2011-09-27 17:55:08 +00:00
Owen Anderson
79c9401e0e
Remove extraneous commit garbage.
...
llvm-svn: 140581
2011-09-26 23:14:02 +00:00
Owen Anderson
7742c81cde
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
...
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
David Meyer
a6e588d80c
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
...
llvm-svn: 140516
2011-09-26 06:13:20 +00:00
Owen Anderson
fc9a0d104c
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
...
llvm-svn: 140426
2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen
ca6877343b
Also match negative offsets for addrmode3 and addrmode5.
...
Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
llvm-svn: 140425
2011-09-23 22:10:33 +00:00
Owen Anderson
e63c963148
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
...
llvm-svn: 140422
2011-09-23 21:57:50 +00:00
Owen Anderson
53c6b08ad8
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
Owen Anderson
071eb7580a
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
Owen Anderson
a2cfbf33af
Revert r140412. This affects more instructions than intended.
...
llvm-svn: 140413
2011-09-23 21:02:01 +00:00
Owen Anderson
227b8c74fb
Thumb2 register-shifted-register loads cannot target the PC or the SP.
...
llvm-svn: 140412
2011-09-23 21:00:32 +00:00
Owen Anderson
22ab29756b
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
...
llvm-svn: 140284
2011-09-21 23:53:44 +00:00
Owen Anderson
7b134fe54c
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
...
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
Owen Anderson
220db2953c
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
...
llvm-svn: 140267
2011-09-21 17:58:45 +00:00
Andrew Trick
c94573ded6
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
...
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
llvm-svn: 140228
2011-09-21 02:20:46 +00:00
Andrew Trick
5b514628ed
whitespace
...
llvm-svn: 140227
2011-09-21 02:17:37 +00:00
Owen Anderson
fbec62c99e
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
...
llvm-svn: 140217
2011-09-21 00:25:23 +00:00
Evan Cheng
ead45e2ba6
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
...
llvm-svn: 140181
2011-09-20 21:38:18 +00:00
Andrew Trick
bfac89c238
Restore hasPostISelHook tblgen flag.
...
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
llvm-svn: 140160
2011-09-20 18:22:31 +00:00
Andrew Trick
53aeb9f663
ARM isel bug fix for adds/subs operands.
...
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
2011-09-20 03:17:40 +00:00
Andrew Trick
43ccb48fb2
whitespace
...
llvm-svn: 140133
2011-09-20 03:06:13 +00:00
Jim Grosbach
e936bdc286
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
...
llvm-svn: 140125
2011-09-20 00:46:54 +00:00
Jim Grosbach
5ca3bddd26
Thumb2 assembly parsing and encoding for USAX.
...
llvm-svn: 140119
2011-09-20 00:30:45 +00:00
Jim Grosbach
882f1ec6d5
Remove incorrect comments. These are not disassmebly only patterns.
...
llvm-svn: 140116
2011-09-20 00:26:34 +00:00
Jim Grosbach
18a65f1fe6
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
...
llvm-svn: 140111
2011-09-20 00:18:52 +00:00
Jim Grosbach
3de5351645
Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.
...
llvm-svn: 140108
2011-09-20 00:10:37 +00:00
Jim Grosbach
dd395f87df
Thumb CPS definition is not disassembler only.
...
llvm-svn: 140106
2011-09-20 00:00:06 +00:00
Jim Grosbach
794028c0e0
Thumb2 range check on CPS mode immediate.
...
llvm-svn: 140105
2011-09-19 23:58:31 +00:00
Owen Anderson
791a17f64a
tMOVSr is not allowed in an IT block either.
...
llvm-svn: 140104
2011-09-19 23:57:20 +00:00
Owen Anderson
3920c43055
CPS instructions are UNPREDICTABLE inside IT blocks.
...
llvm-svn: 140102
2011-09-19 23:47:10 +00:00
Jim Grosbach
011bd172ea
Tidy up comments.
...
llvm-svn: 140099
2011-09-19 23:38:34 +00:00
Jim Grosbach
2341e082fc
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
...
llvm-svn: 140095
2011-09-19 23:31:02 +00:00
Jim Grosbach
dd8d66f3aa
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
...
llvm-svn: 140088
2011-09-19 23:13:25 +00:00
Jim Grosbach
a5a28c45e5
Thumb2 assembly parsing and encoding for UASX.
...
llvm-svn: 140085
2011-09-19 23:05:22 +00:00
Owen Anderson
25138827ef
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
...
llvm-svn: 140079
2011-09-19 22:34:23 +00:00
Jim Grosbach
6da9e6b23d
Thumb2 assembly parsing and encoding for TBB/TBH.
...
llvm-svn: 140078
2011-09-19 22:21:13 +00:00
Jim Grosbach
207a337a60
Tidy up a bit.
...
llvm-svn: 140050
2011-09-19 20:31:59 +00:00
Jim Grosbach
c7fa5f0c00
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
...
llvm-svn: 140047
2011-09-19 20:29:33 +00:00
Owen Anderson
4bf9e290e9
Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
...
llvm-svn: 140041
2011-09-19 20:00:02 +00:00
Jim Grosbach
57328aa902
ARM asm parsing should handle pre-indexed writeback w/o immediate.
...
For example, 'ldrb r9, [sp]!' is odd, but valid.
llvm-svn: 140035
2011-09-19 18:42:21 +00:00
Owen Anderson
b843f3625d
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
...
llvm-svn: 140032
2011-09-19 18:07:10 +00:00
Jim Grosbach
c677995374
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
...
llvm-svn: 140029
2011-09-19 17:56:37 +00:00
Owen Anderson
c1f638997d
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
...
llvm-svn: 139972
2011-09-16 23:30:01 +00:00
Owen Anderson
aec67a3ea1
Fix bitfield decoding based on Eli's feedback.
...
llvm-svn: 139969
2011-09-16 23:04:48 +00:00
Jim Grosbach
95242bff08
Thumb2 assembly parsing and encoding for SUB(immediate).
...
llvm-svn: 139966
2011-09-16 22:58:42 +00:00
Owen Anderson
5d23e1e5b4
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
...
llvm-svn: 139965
2011-09-16 22:42:36 +00:00
Owen Anderson
eae0eee720
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
...
llvm-svn: 139964
2011-09-16 22:29:48 +00:00
Owen Anderson
3a487c8c9b
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
...
llvm-svn: 139958
2011-09-16 22:17:02 +00:00
Jim Grosbach
d521731d40
Thumb2 assembly parsing and encoding for STR.
...
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
llvm-svn: 139949
2011-09-16 21:55:56 +00:00
Jim Grosbach
371c88528b
Tidy up. 80 columns.
...
llvm-svn: 139944
2011-09-16 21:09:00 +00:00
Owen Anderson
5804085f26
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
...
llvm-svn: 139943
2011-09-16 21:08:33 +00:00
Jim Grosbach
916a6c71aa
Thumb2 assembly parsing and encoding for STR(immediate).
...
Add aliases for STRB/STRH while there. Tests forthcoming for those.
llvm-svn: 139942
2011-09-16 21:06:12 +00:00
Jim Grosbach
13af7198d5
Thumb2 assembly parsing and encoding for STMIA.
...
llvm-svn: 139938
2011-09-16 20:50:13 +00:00
Jim Grosbach
47ff106753
Thumb2 assembly parsing and encoding for SSAX.
...
llvm-svn: 139929
2011-09-16 18:37:10 +00:00
Jim Grosbach
6f6453f64b
Thumb2 assembly parsing and encoding for SSAT.
...
llvm-svn: 139926
2011-09-16 18:32:30 +00:00
Jim Grosbach
5a8b63fe51
Thumb2 assembly parsing and encoding for SRS.
...
llvm-svn: 139925
2011-09-16 18:25:22 +00:00
Jim Grosbach
0f1615c381
Thumb2 assembly parsing and encoding for SMMULL.
...
llvm-svn: 139921
2011-09-16 18:05:48 +00:00
Jim Grosbach
3c3a9393ab
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
...
llvm-svn: 139909
2011-09-16 17:10:44 +00:00
Jim Grosbach
9e471afd9c
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
...
llvm-svn: 139906
2011-09-16 16:58:03 +00:00
Jim Grosbach
f41c168102
Kill some dead code.
...
llvm-svn: 139904
2011-09-16 16:45:40 +00:00
Jim Grosbach
94fec9618a
Tidy up a bit.
...
llvm-svn: 139903
2011-09-16 16:39:25 +00:00
Jim Grosbach
d382581509
Thumb2 assembly parsing and encoding for SMLAL.
...
llvm-svn: 139902
2011-09-16 16:38:00 +00:00
Jim Grosbach
27a086b1d0
Remove incorrect comments.
...
llvm-svn: 139877
2011-09-15 23:45:50 +00:00
Owen Anderson
e54c4beb5a
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
...
llvm-svn: 139876
2011-09-15 23:38:46 +00:00
Jim Grosbach
423aae30b2
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
...
llvm-svn: 139870
2011-09-15 22:34:29 +00:00
Eli Friedman
0e654e52d9
Minor cleanup.
...
llvm-svn: 139869
2011-09-15 22:26:18 +00:00
Eli Friedman
1df4766bda
Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1.
...
llvm-svn: 139865
2011-09-15 22:18:49 +00:00
Jim Grosbach
1ac9dd8a72
Thumb2 assembly parsing and encoding for SASX.
...
llvm-svn: 139843
2011-09-15 21:01:23 +00:00
Jim Grosbach
553692fcce
Thumb2 assembly parsing and encoding for RSB.
...
llvm-svn: 139839
2011-09-15 20:54:14 +00:00
Jim Grosbach
50ee930e9a
Thumb2 assembly parsing and encoding for REV16/REVSH.
...
llvm-svn: 139828
2011-09-15 19:46:13 +00:00
Owen Anderson
84d4e5d0e2
Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
...
llvm-svn: 139820
2011-09-15 18:36:29 +00:00
Jim Grosbach
9d7aa9bcbc
Thumb2 assembly parsing and encoding for REV.
...
llvm-svn: 139813
2011-09-15 18:13:30 +00:00
Jim Grosbach
69ddec5ff7
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.'
...
llvm-svn: 139796
2011-09-15 16:16:50 +00:00
Jim Grosbach
d428c970e3
Thumb2 push/pop mnemonic recognition.
...
llvm-svn: 139794
2011-09-15 15:55:04 +00:00
Jim Grosbach
669e269758
Thumb2 assembly parsing and encoding for PKH.
...
llvm-svn: 139754
2011-09-14 23:16:41 +00:00
Jim Grosbach
c1475b0f3f
ARMv7a has the PKH instructions.
...
llvm-svn: 139753
2011-09-14 23:16:34 +00:00
Jim Grosbach
1a4f264f52
ARM tighten up the register classes for the PKH instructions.
...
llvm-svn: 139748
2011-09-14 22:52:14 +00:00
Owen Anderson
86f1fb2955
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
...
llvm-svn: 139747
2011-09-14 22:46:14 +00:00
Jim Grosbach
e841adae12
Thumb2 assembly parsing and encoding for MVN.
...
llvm-svn: 139739
2011-09-14 21:24:41 +00:00
Owen Anderson
04d8803035
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
...
llvm-svn: 139736
2011-09-14 21:06:21 +00:00
Jim Grosbach
585e3c779f
Thumb2 assembly parsing and encoding for MUL.
...
llvm-svn: 139735
2011-09-14 21:00:40 +00:00
Jim Grosbach
b1c70aab3e
Thumb2 assembly parsing and encoding for MSR/MRS.
...
Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
Jim Grosbach
932d409524
Thumb2 assembly parsing for MOV in IT block.
...
Select the right 16 vs. 32 bit encoding in an IT block.
llvm-svn: 139714
2011-09-14 19:12:11 +00:00
Jim Grosbach
41c8bdfdd9
ARM fix assembly parser handling of ranges in register lists.
...
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
llvm-svn: 139707
2011-09-14 18:08:35 +00:00
Jim Grosbach
b2ddf62001
Remove unnecessary scope resolution operator.
...
llvm-svn: 139656
2011-09-13 22:56:44 +00:00
Owen Anderson
d0121fe635
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
...
llvm-svn: 139639
2011-09-13 20:46:26 +00:00
Jim Grosbach
90b78a6f1f
There's only 16 regs legal in a register list.
...
llvm-svn: 139637
2011-09-13 20:35:57 +00:00
Jim Grosbach
74f96e7f3c
Tidy up a few 80 column violations.
...
llvm-svn: 139636
2011-09-13 20:30:37 +00:00
Jim Grosbach
a04c99bca5
Tidy up a bit.
...
llvm-svn: 139635
2011-09-13 20:27:44 +00:00
Owen Anderson
b4ed08c465
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
...
llvm-svn: 139610
2011-09-13 17:59:19 +00:00
Owen Anderson
5982d4d51b
Fix encoding of Thumb2 shifted register operands with RRX shifts.
...
llvm-svn: 139606
2011-09-13 17:34:32 +00:00
Eli Friedman
c6ff621dc5
Zap some junk from the ARM instruction descriptions.
...
llvm-svn: 139575
2011-09-13 02:29:58 +00:00
Jim Grosbach
0b277b24ea
Tidy up a bit.
...
llvm-svn: 139559
2011-09-12 23:36:42 +00:00
Owen Anderson
a1a10ed5c6
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
...
llvm-svn: 139542
2011-09-12 21:28:46 +00:00
Owen Anderson
0081444d87
Fix encoding of PC-relative LDRSHW with an immediate offset.
...
llvm-svn: 139537
2011-09-12 20:36:51 +00:00
Owen Anderson
b1d401e514
There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
...
llvm-svn: 139531
2011-09-12 20:07:22 +00:00
Owen Anderson
05ef2c122d
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
Jim Grosbach
52492b1cf3
Thumb2 parsing and encoding for MOV(immediate).
...
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
Owen Anderson
9cd21ce8c9
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
Owen Anderson
ca4447e808
Fix an ambiguously nested if.
...
llvm-svn: 139431
2011-09-09 23:13:02 +00:00
Owen Anderson
58bb862098
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
...
llvm-svn: 139429
2011-09-09 23:05:14 +00:00
Owen Anderson
dbe77fc5a1
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
Owen Anderson
a7838cb723
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
...
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
Jim Grosbach
6225a96bf5
Thumb2 assembly parsing and encoding for MLA and MLS.
...
llvm-svn: 139399
2011-09-09 20:24:45 +00:00
Jim Grosbach
915ba5189e
Thumb2 assembly parsing and encoding for LDRSB.
...
llvm-svn: 139389
2011-09-09 19:42:40 +00:00
Jim Grosbach
eb2d668899
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
...
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
Owen Anderson
99ad1a853e
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
...
llvm-svn: 139329
2011-09-08 22:48:37 +00:00
Owen Anderson
d7127e0c27
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
...
llvm-svn: 139328
2011-09-08 22:42:49 +00:00
Jim Grosbach
9f150bfedf
Thumb2 assembly parsing and encoding for LDRD(immediate).
...
Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
Jim Grosbach
5ac3aa158b
Thumb2 assembly parsing and encoding for LDR post-indexed.
...
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
llvm-svn: 139272
2011-09-08 01:01:32 +00:00
Jim Grosbach
1aa191032a
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
...
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
llvm-svn: 139270
2011-09-08 00:39:19 +00:00
Owen Anderson
4a5ec6836f
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
...
llvm-svn: 139268
2011-09-08 00:11:18 +00:00
Jim Grosbach
8b54d19514
Thumb2 assembly parsing and encoding for LDRBT.
...
llvm-svn: 139267
2011-09-07 23:39:14 +00:00
Jim Grosbach
a3ff9eeb85
Thumb2 assembly parsing and encoding for LDR(register).
...
llvm-svn: 139264
2011-09-07 23:10:15 +00:00
Jim Grosbach
d640c62856
Thumb2 assembly parsing and encoding for LDRB(immediate).
...
llvm-svn: 139258
2011-09-07 21:41:25 +00:00
Owen Anderson
26467730c1
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
...
llvm-svn: 139256
2011-09-07 21:10:42 +00:00
Jim Grosbach
20642fb479
Thumb2 parsing and encoding for LDR(immediate).
...
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
llvm-svn: 139254
2011-09-07 20:58:57 +00:00
Jim Grosbach
054b346e46
Thumb2 parsing and encoding for LDMDB.
...
llvm-svn: 139251
2011-09-07 19:57:53 +00:00
James Molloy
ac057f13a5
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
...
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
Jim Grosbach
bd018fd94f
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
...
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
llvm-svn: 139243
2011-09-07 18:39:47 +00:00
Jim Grosbach
20689d28e7
Thumb2 parsing and encoding for LDMIA.
...
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
llvm-svn: 139242
2011-09-07 18:05:34 +00:00
Owen Anderson
4106b9fb31
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
James Molloy
f781d3d8e9
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
...
llvm-svn: 139237
2011-09-07 17:24:38 +00:00
Jim Grosbach
c0ebdea61f
Thumb2 use 'ldm' as default mnemonic.
...
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
llvm-svn: 139234
2011-09-07 16:22:42 +00:00
Jim Grosbach
7969f880c0
Better diagnostic location information for mnemonic suffices.
...
llvm-svn: 139232
2011-09-07 16:06:04 +00:00