RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
Code Issues Projects Releases Wiki Activity
35,436 Commits 4 Branches 5 Tags 704 MiB
7627a7d8f4
Commit Graph

726 Commits

Author SHA1 Message Date
Chris Lattner
8afa040b03 Really add support for compilers without noinline 
llvm-svn: 29491
 2006-08-03 00:26:13 +00:00
Evan Cheng
64b9364083 Pass N by reference to select functions to prevent gcc from allocating more stack. 
llvm-svn: 29423
 2006-08-01 01:07:48 +00:00
Evan Cheng
1335c08549 Remove an unneeded match condition: the type check for root node has been 
moved to outside the actual select routine.

llvm-svn: 29415
 2006-07-31 19:01:58 +00:00
Evan Cheng
09f9f995f5 Split each select function for a particular opcode into multiple ones. One 
per possible ValueType of the node. e.g. Select_add is split into Select_add_i8,
Select_add_i16, etc.

For opcodes which do not produce a non-chain result, it is split on the
ValueType of its first non-chain operand. e.g. Select_store.

On X86 / Mac OS X, Select_store used to be the largest function. It had a stack
frame size of 8.5k. Now the largest one is Store_i32 with a frame size of 3.1k.

llvm-svn: 29404
 2006-07-28 22:51:01 +00:00
Evan Cheng
1ffea6db32 Clean up. 
llvm-svn: 29378
 2006-07-28 01:19:22 +00:00
Evan Cheng
5f0e94c299 Rename IsFoldableBy to CanBeFoldedleBy 
llvm-svn: 29376
 2006-07-28 01:03:48 +00:00
Evan Cheng
3b5f1c6248 Remove InFlightSet hack. No longer needed. 
llvm-svn: 29373
 2006-07-28 00:47:19 +00:00
Evan Cheng
35cdbdb796 Remove dead code. 
llvm-svn: 29359
 2006-07-27 19:59:34 +00:00
Evan Cheng
1e640aeee8 Let each target specific isel provide routine to check if a chain producing node is foldable by another. 
llvm-svn: 29335
 2006-07-27 06:36:49 +00:00
Evan Cheng
978280e425 Fix for bug 840. Only use noinline attribute if gcc version >= 3.4 
llvm-svn: 29311
 2006-07-26 23:06:27 +00:00
Evan Cheng
a80a26a5f8 Removed a hack intended to allow (store (op (load))) folding. Will handle this with preprocessing. 
llvm-svn: 29258
 2006-07-21 22:19:51 +00:00
Jim Laskey
085a8477a7 Eliminate data relocations by using NULL instead of global empty list. 
llvm-svn: 29250
 2006-07-21 21:15:20 +00:00
Jim Laskey
a67adda697 Use an enumeration to eliminate data relocations. 
llvm-svn: 29249
 2006-07-21 20:57:35 +00:00
Evan Cheng
94c6f2c3b5 Also checks for noResults field. 
llvm-svn: 29235
 2006-07-20 23:36:20 +00:00
Evan Cheng
0675bc6539 Make sub- and super- register classes const. 
llvm-svn: 29200
 2006-07-19 05:58:18 +00:00
Chris Lattner
8d82c97338 Fix a bug handling instructions, like blr, which just consist of a text 
string.  The return value of printInstruction should be true for these.

llvm-svn: 29196
 2006-07-19 01:39:06 +00:00
Evan Cheng
abd650f034 Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
llvm-svn: 29193
 2006-07-19 00:24:41 +00:00
Evan Cheng
708ca90182 Make sub- super- reg-class tables static. 
llvm-svn: 29190
 2006-07-18 22:18:31 +00:00
Chris Lattner
4ec74164ba Fix case where identical cases were not detected across case #0, because 
instructions not handled would have a case value of #0, throwing things off.
This marginally shrinks the X86 asmprinter, but shrinks the sparc asmwriter
by 25 lines.

llvm-svn: 29187
 2006-07-18 19:27:30 +00:00
Chris Lattner
77571f3b5e Fix an accidentally duplicated line that caused tblgen to crash on itanium. 
Add an assert that catches the real problem earlier.

llvm-svn: 29185
 2006-07-18 19:06:01 +00:00
Chris Lattner
7ee758d987 Maximally group commands. When all instructions within a command set have a 
series of identical commands, handle them all with one switch.  In the case
of the x86 at&t asm printer, only 3 switches are needed for all instructions.

llvm-svn: 29184
 2006-07-18 18:28:27 +00:00
Chris Lattner
5ea6af7b07 Change generator to remove operands as it processes them. No change in 
generated file.

llvm-svn: 29183
 2006-07-18 17:56:07 +00:00
Chris Lattner
39569f417f Handle the last operand more intelligently. When emitting the \n, also 
return from the asmprinter to make the generated asmprinter both more
efficient and smaller.

llvm-svn: 29182
 2006-07-18 17:50:22 +00:00
Chris Lattner
2c14435831 Emit switches with 1/2 cases as unconditional code or an if/then/else for 
tidyness.

llvm-svn: 29181
 2006-07-18 17:43:54 +00:00
Chris Lattner
b84950e599 Steal bits from the asm string index to use for operand information. On both 
x86 and ppc, this gets us 4 more bits to play with, since the string indices
both only use 12 bits.

llvm-svn: 29180
 2006-07-18 17:38:46 +00:00
Chris Lattner
c4f6ee6c6d Merge operand info and asmstr idx into a single 32-bit field. No other change. 
llvm-svn: 29179
 2006-07-18 17:32:27 +00:00
Chris Lattner
12ac6ac958 Completely change the structure of the generated asmprinter to be more table 
based and less switch-statements-with-hundreds-of-cases based.  This shrinks
the x86 asmprinters to about 1/3 their previous size.

Other improvements coming.

llvm-svn: 29177
 2006-07-18 17:18:03 +00:00
Evan Cheng
1910357655 Use __attribute__((noinline)) only if compiled by gcc. 
llvm-svn: 29161
 2006-07-16 06:14:37 +00:00
Evan Cheng
22ef77c90c Parameterize target node ValueType to allow more sharing of emit functions. 
Also reduce the number of arguments passed to emit functions and removed a
hack.

llvm-svn: 29160
 2006-07-16 06:12:52 +00:00
Evan Cheng
ff3dc2868c Reduce instruction selection code size and stack frame size by factoring 
code that emit target specific nodes into emit functions that are uniquified
and shared among selection routines.
e.g. This reduces X86ISelDAGToDAG.o (release) from ~2M to ~1.5M. Stack frame
size of Select_store from ~13k down to ~8k.
This is the first step. Further work to enable more sharing will follow.

llvm-svn: 29158
 2006-07-15 08:45:20 +00:00
Chris Lattner
6c71767f88 The generated index array should be const. 
llvm-svn: 29155
 2006-07-14 23:14:02 +00:00
Chris Lattner
e6892852be Emit the string information for the asm writer as a single large string 
and index into it, instead of emitting it like this:

  static const char * const OpStrs[] = {
    "PHINODE\n",        // PHI
    0,  // INLINEASM
    "adc ",     // ADC32mi
    "adc ",     // ADC32mi8
   ...

The old way required thousands of relocations that slows down link time and
dynamic load times.

This also cuts about 10K off each of the X86 asmprinters, and should shrink
the others as well.

llvm-svn: 29152
 2006-07-14 22:59:11 +00:00
Jim Laskey
a140e5e06c Clean up. 
llvm-svn: 29137
 2006-07-13 22:17:08 +00:00
Jim Laskey
a96045b549 1. Simplfy bit operations. 
2. Coalesce instruction cases.

llvm-svn: 29135
 2006-07-13 21:02:53 +00:00
Jim Laskey
e3cc434032 Move base value of instruction to lookup table to prepare for case reduction. 
llvm-svn: 29122
 2006-07-12 19:15:43 +00:00
Jim Laskey
d19ba2cf6c It was pointed out that DEBUG() is only available with -debug. 
llvm-svn: 29106
 2006-07-11 18:25:13 +00:00
Jim Laskey
4c0d841280 Ensure that dump calls that are associated with asserts are removed from 
non-debug build.

llvm-svn: 29105
 2006-07-11 17:58:07 +00:00
Jim Laskey
9b46a1235a Reduce bloat in target libraries by removing per machine instruction assertion 
from code emitter generation.

llvm-svn: 29097
 2006-07-11 01:25:59 +00:00
Chris Lattner
28cf368f82 tblgen uses EH 
llvm-svn: 29034
 2006-07-07 00:21:17 +00:00
Evan Cheng
90a25bcd6f Ugly hack! Add helper functions InsertInFlightSetEntry and 
RemoveInFlightSetEntry. They are used in place of direct set operators to
reduce instruction selection function stack size.

llvm-svn: 28987
 2006-06-29 23:57:05 +00:00
Chris Lattner
093d9771df Fix an error message regression. Print: 
LI8:    (LI8:i64 (imm:i64):$imm)
instead of:
  LI8:    (LI8:MVT::i64 (imm:MVT::i64):$imm)

llvm-svn: 28868
 2006-06-20 00:56:37 +00:00
Chris Lattner
88f2956ac8 Don't require src/dst patterns to be able to fully resolve their types, 
because information about one can help refine the other.  This allows us to
write:

def : Pat<(i32 (extload xaddr:$src, i8)),
          (LBZX xaddr:$src)>;

as:

def : Pat<(extload xaddr:$src, i8),
          (LBZX xaddr:$src)>;

because tblgen knows LBZX returns i32.

llvm-svn: 28865
 2006-06-20 00:31:27 +00:00
Chris Lattner
25273f71bf Make sure to use the result of the pattern to infer the result type of the 
instruction, and the result type of the instruction to refine the pattern.
This allows us to write things like this:

def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;

as:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (VR128:$src)>

and fixes a ppc64 issue.

llvm-svn: 28863
 2006-06-20 00:18:02 +00:00
Chris Lattner
dfcd07cc4c Improve a comment. 
llvm-svn: 28833
 2006-06-16 18:25:06 +00:00
Evan Cheng
07d8ccec50 Instructions with variable operands (variable_ops) can have a number required 
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
 2006-06-15 07:22:16 +00:00
Evan Cheng
3d60e7e72b Allow more use of iPTR in patterns. 
llvm-svn: 28790
 2006-06-15 00:16:37 +00:00
Evan Cheng
434153a2b4 Added support for variable_ops. 
llvm-svn: 28788
 2006-06-14 22:22:20 +00:00
Evan Cheng
191886d10f Fix support for optional input flag. 
llvm-svn: 28784
 2006-06-14 19:27:50 +00:00
Evan Cheng
fe3e6e1967 getOperandNum(): error if specified operand number is out of range. 
llvm-svn: 28775
 2006-06-13 21:47:27 +00:00
Chris Lattner
f506d91be6 Wrap to 80 cols 
llvm-svn: 28743
 2006-06-09 23:59:44 +00:00
Reid Spencer
00ee1dc6ea Don't build tblgen with -pedantic or -Wno-long-long 
llvm-svn: 28638
 2006-06-01 18:20:23 +00:00
Evan Cheng
1e9556ee06 Can't trust NodeDepth when checking for possibility of load folding creating 
a cycle. This increase the search space and will increase compile time (in
practice it appears to be small, e.g. 176.gcc goes from 62 sec to 65 sec)
that will be addressed later.

llvm-svn: 28476
 2006-05-25 20:16:55 +00:00
Evan Cheng
2a4c04d35a Fixed a really ugly bug. The TableGen'd isel is not freeing the "inflight set" 
correctly. That is causing non-deterministic behavior (and possibly preventing
some load folding from happening).

llvm-svn: 28458
 2006-05-25 00:21:44 +00:00
Chris Lattner
b3aa8ccfe0 Don't make zero-sized static arrays 
llvm-svn: 28448
 2006-05-24 17:31:02 +00:00
Chris Lattner
f604017e47 Patches to make the LLVM sources more -pedantic clean. Patch provided 
by Anton Korobeynikov!  This is a step towards closing PR786.

llvm-svn: 28447
 2006-05-24 17:04:05 +00:00
Evan Cheng
accb9d0378 Now that iPTR is a fully resolved type. We end up losing the type check for 
patterns that look like this:

def : Pat<(i32 (X86Wrapper tconstpool  :$dst)), (MOV32ri tconstpool  :$dst)>;

InsertOneTypeCheck should copy the type from the resolved pattern to the
unresolved one as long as there types are different.

llvm-svn: 28389
 2006-05-19 07:24:32 +00:00
Evan Cheng
00c1318055 lib/Target/Target.td 
llvm-svn: 28386
 2006-05-18 20:42:07 +00:00
Evan Cheng
fcdfdcaa96 Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore. 
llvm-svn: 28376
 2006-05-18 00:08:46 +00:00
Evan Cheng
3cfed5af84 Typo 
llvm-svn: 28366
 2006-05-17 20:55:51 +00:00
Evan Cheng
5dc3e33623 Remove PointerType from target definition. Use abstract type MVT::iPTR to 
represent pointer type.

llvm-svn: 28363
 2006-05-17 20:37:59 +00:00
Evan Cheng
d4a056116c Allow patterns to refer to physical registers that belong to multiple 
register classes.

llvm-svn: 28323
 2006-05-16 07:05:30 +00:00
Evan Cheng
409dd126bf Noop instruction 
llvm-svn: 28241
 2006-05-12 07:47:00 +00:00
Evan Cheng
3d1e1ffd9b Unused instruction 
llvm-svn: 28240
 2006-05-12 07:42:01 +00:00
Evan Cheng
d6549daf76 Also add super- register classes info. 
llvm-svn: 28221
 2006-05-11 07:30:26 +00:00
Evan Cheng
2af8a9f980 Watch out for the following case: 
1. Use expects a chain output.
2. Node is expanded into multiple target ops.
3. One of the inner node produces a chain, the outer most one doesn't.

llvm-svn: 28209
 2006-05-10 02:47:57 +00:00
Evan Cheng
0655b538d6 Fix a load folding bug. It is exposed by a multi- resulting instructions 
def : Pat<> pattern.

llvm-svn: 28208
 2006-05-10 00:05:46 +00:00
Evan Cheng
87b66b9aec Add sub-register class information. 
llvm-svn: 28195
 2006-05-09 06:34:26 +00:00
Evan Cheng
ca3dc213dc Set isStore of instructions with ISD::TRUNCSTORE root node. 
llvm-svn: 28075
 2006-05-03 02:08:34 +00:00
Chris Lattner
8cbad2f76a Put instruction names into the first non TargetInstrInfo namespace found. 
llvm-svn: 28043
 2006-05-01 23:46:16 +00:00
Chris Lattner
da6162633a instructions can be in different namespaces. Make sure to use the right 
one for each instruction.

llvm-svn: 28038
 2006-05-01 17:01:17 +00:00
Evan Cheng
0bae850dda Formating 
llvm-svn: 28036
 2006-05-01 09:30:17 +00:00
Evan Cheng
efcb0061df Mark instructions whose pattern is (store ...) isStore. 
llvm-svn: 28032
 2006-05-01 09:04:20 +00:00
Evan Cheng
9f21c2daf4 Remove the temporary option: -no-isel-fold-inflight 
llvm-svn: 28012
 2006-04-28 18:54:11 +00:00
Evan Cheng
3466555d87 When isel'ing a node, mark its operands "InFlight" before selecting them. These 
nodes should not be folded into other nodes.
This fixes the miscompilation of PR 749.
Temporarily under flag control.

llvm-svn: 28002
 2006-04-28 02:08:10 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner
56e4ca77c6 Don't fill in fields that no longer exist. 
llvm-svn: 27898
 2006-04-20 18:32:22 +00:00
Evan Cheng
adc5e703ca Rename AddedCost to AddedComplexity. 
llvm-svn: 27841
 2006-04-19 20:36:09 +00:00
Evan Cheng
318120f8ad Allow "let AddedCost = n in" to increase pattern complexity. 
llvm-svn: 27834
 2006-04-19 18:07:24 +00:00
Reid Spencer
599a575d0e Add missing things to the distribution. 
llvm-svn: 27650
 2006-04-13 06:27:20 +00:00
Chris Lattner
1659f983ff Fix a typo: Instr* -> Intr* 
llvm-svn: 27568
 2006-04-10 22:02:59 +00:00
Chris Lattner
9f8d5b538e Infer element types for shuffle masks 
llvm-svn: 27456
 2006-04-06 20:36:51 +00:00
Chris Lattner
7f54d730f1 rename a method, to avoid confusion with llvm intrinsics. 
llvm-svn: 27455
 2006-04-06 20:19:52 +00:00
Chris Lattner
9eacf6b01c Adjust the Intrinsics.gen interface a little bit 
llvm-svn: 27345
 2006-04-02 03:35:30 +00:00
Chris Lattner
914742aa1e regenerate 
llvm-svn: 27313
 2006-03-31 21:54:11 +00:00
Chris Lattner
5fabd2c311 Generalize the previous binary operator support and add a string concatenation 
operation.  This implements Regression/TableGen/strconcat.td.

llvm-svn: 27312
 2006-03-31 21:53:49 +00:00
Chris Lattner
ef86937943 Allow bits init values to be used in patterns, turn them into ints. 
llvm-svn: 27286
 2006-03-31 05:25:56 +00:00
Chris Lattner
f9e5ac8c9a Final bugfix for PR724. GCC won't inline varargs functions, so use one to 
validate the prototype of intrinsic functions.  This prevents GCC from going
crazy and inlining too much stuff, eventually running out of memory.

llvm-svn: 27283
 2006-03-31 04:48:26 +00:00
Chris Lattner
7ae6895610 When emitting code for the verifier, instead of emitting each case statement 
independently, batch up checks so that identically typed intrinsics share
verifier code.  This dramatically reduces the size of the verifier function,
which should help avoid GCC running out of memory compiling Verifier.cpp.

llvm-svn: 27281
 2006-03-31 04:24:58 +00:00
Chris Lattner
8fd532e8a4 regenerate 
llvm-svn: 27264
 2006-03-30 22:51:12 +00:00
Chris Lattner
39d2d17cb3 Implement Regression/TableGen/DagDefSubst.ll 
llvm-svn: 27263
 2006-03-30 22:50:40 +00:00
Evan Cheng
86b5b7cf18 Don't sort the names before outputing the intrinsic name table. It causes a 
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)

llvm-svn: 27237
 2006-03-28 22:25:56 +00:00
Chris Lattner
723cb246c9 Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. 
Also, don't emit dynamic checks when we can compute them statically

llvm-svn: 27202
 2006-03-28 00:41:33 +00:00
Chris Lattner
424516c95a Only compute intrinsic valuetypes when in a target .td file. 
llvm-svn: 27197
 2006-03-28 00:15:00 +00:00
Chris Lattner
8a2ffaea1d revert this, it breaks things. 
llvm-svn: 27196
 2006-03-28 00:03:08 +00:00
Chris Lattner
50f432af88 Add support for decoding iPTR to the right pointer type. 
llvm-svn: 27188
 2006-03-27 22:48:18 +00:00
Chris Lattner
a092011a5c Print error messages like this: 
tblgen: In STVEBX: Intrinsic 'llvm.ppc.altivec.stvebx' expects 3 operands, not 2 operands!

instead of like this:
tblgen: In STVEBX: Intrinsic 'intrinsic_void expects 3 operands, not 2 operands!

llvm-svn: 27185
 2006-03-27 22:21:18 +00:00
Chris Lattner
ed2f2220da Add a missing check which cause an invalid .td file to crash tblgen 
llvm-svn: 27126
 2006-03-25 22:12:44 +00:00
Chris Lattner
e7a3b00d6a When failing selection for an intrinsic, print this: 
Cannot yet select: intrinsic %llvm.ppc.altivec.lvx

instead of this:

Cannot yet select: 0x9b047e0: v4i32,ch = INTRINSIC 0x9b04540:1, 0x9b04710, 0x9b04790, 0x9b04540

llvm-svn: 27110
 2006-03-25 06:47:53 +00:00
Chris Lattner
de644c5e88 Change approach so that we get codegen for free for intrinsics. With this, 
intrinsics that don't take pointer arguments now work.  For example, we can
compile this:

int test3( __m128d *A) {
  return _mm_movemask_pd(*A);
}
int test4( __m128 *A) {
  return _mm_movemask_ps(*A);
}

to this:

_test3:
        movl 4(%esp), %eax
        movapd (%eax), %xmm0
        movmskpd %xmm0, %eax
        ret
_test4:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        movmskps %xmm0, %eax
        ret

llvm-svn: 27090
 2006-03-24 23:10:39 +00:00
Chris Lattner
d054091a40 fix 80 column violations 
llvm-svn: 27084
 2006-03-24 21:52:20 +00:00
Chris Lattner
92a040dbbf Parse intrinsics correctly and perform type propagation. This doesn't currently 
emit the code to select intrinsics, but that is next :)

llvm-svn: 27082
 2006-03-24 21:48:51 +00:00
Jim Laskey
1716e53341 Add dwarf register numbering to register data. 
llvm-svn: 27081
 2006-03-24 21:15:58 +00:00
Chris Lattner
f91acdb005 Make sure to initialize the TheDef field! 
llvm-svn: 27078
 2006-03-24 20:25:01 +00:00
Chris Lattner
522211a435 Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of 
the CodeGen* implementations.

Parse the MVT::ValueType for each operand of the intrinsics.

llvm-svn: 27075
 2006-03-24 19:49:31 +00:00
Chris Lattner
e6a8522990 extract some more information from the intrinsic table 
llvm-svn: 27022
 2006-03-24 01:13:55 +00:00
Reid Spencer
825547e65e Add new generated files to be ignored. 
llvm-svn: 27011
 2006-03-23 23:45:32 +00:00
Evan Cheng
b632a1d0d5 Allow result node to be a simple leaf node. This enable bitconvert patterns 
like this:
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;

llvm-svn: 26968
 2006-03-23 02:35:32 +00:00
Evan Cheng
d21f479c5f Don't forget to promote xform function to an explicit node for def : Pat<> 
patterns.

llvm-svn: 26929
 2006-03-21 20:44:17 +00:00
Chris Lattner
4da595f4c8 minor code simplification 
llvm-svn: 26918
 2006-03-21 06:42:58 +00:00
Evan Cheng
e87add642d The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't 
one, i.e. don't select it.

llvm-svn: 26909
 2006-03-20 22:53:06 +00:00
Evan Cheng
38a1075865 It should be ok for a xform output type to be different from input type. 
llvm-svn: 26899
 2006-03-20 08:09:17 +00:00
Evan Cheng
f0effde00d Copy matching pattern's output type info to instruction result pattern. 
The instruction patterns do not contain enough information to resolve the
exact type of the destination if it of a generic vector type.

llvm-svn: 26892
 2006-03-20 06:04:09 +00:00
Chris Lattner
eb65663732 Add a new SDTCisIntVectorOfSameSize type constraint 
llvm-svn: 26890
 2006-03-20 05:39:48 +00:00
Evan Cheng
a1f9db3ad4 getEnumName() missed v8i8, v4i16, and v2i32 types 
llvm-svn: 26869
 2006-03-19 07:57:34 +00:00
Chris Lattner
d7cabc0f81 Fix miscodegen of V_SET0 in PPC. 
llvm-svn: 26836
 2006-03-18 00:40:36 +00:00
Chris Lattner
6c339fec5a allow the GCCBuiltinName field to be optional 
llvm-svn: 26784
 2006-03-15 19:15:26 +00:00
Jeff Cohen
4bf914ebcc Fix VC++ build error. 
llvm-svn: 26773
 2006-03-15 02:51:05 +00:00
Chris Lattner
0339c2ab58 remove typo 
llvm-svn: 26772
 2006-03-15 02:05:38 +00:00
Chris Lattner
bbca65b845 Autogenerate a table of intrinsic names, so we can map from intrinsic ID to 
LLVM intrinsic function name.

llvm-svn: 26771
 2006-03-15 01:55:21 +00:00
Chris Lattner
697e830c63 Autogenerate code to map from GCC builtin to LLVM intrinsic. 
llvm-svn: 26770
 2006-03-15 01:33:26 +00:00
Reid Spencer
13a38e914a Add a newline at the end to avoid gcc warnings. 
llvm-svn: 26749
 2006-03-14 05:59:52 +00:00
Chris Lattner
ecc2db9f6d emit a mapping from LLVM intrinsic -> GCC builtins. 
llvm-svn: 26736
 2006-03-13 23:08:44 +00:00
Chris Lattner
5efaeff492 Verify that packed type operands have the right size and base type. 
llvm-svn: 26735
 2006-03-13 22:38:57 +00:00
Chris Lattner
8930c740ac fix pasto in generate assertion msg 
llvm-svn: 26706
 2006-03-11 00:20:47 +00:00
Chris Lattner
fa0acde009 generate side-effect info 
llvm-svn: 26672
 2006-03-09 22:37:52 +00:00
Chris Lattner
67900dea61 Parse mod/ref properties, autogen mod/ref information 
llvm-svn: 26669
 2006-03-09 22:30:49 +00:00
Chris Lattner
35d32c232a parse intrinsic types 
autogenerate an intrinsic verifier

llvm-svn: 26666
 2006-03-09 22:05:04 +00:00
Chris Lattner
f4bb4b3b11 autogenerate the function name recognizer 
llvm-svn: 26663
 2006-03-09 20:34:19 +00:00
Evan Cheng
df3c89dd52 Temporary hack to enable more (store (op (load ...))) folding. This makes 
it possible when a TokenFactor is between the load and store. But is still
missing some cases due to ordering issue.

llvm-svn: 26638
 2006-03-09 08:19:11 +00:00
Evan Cheng
71c62ae1f4 Don't generate silly matching code like this: 
if (N1.getOpcode() == ISD::ADD &&
     ...)
   if (... &&
       (N1.getNumOperands() == 1 || !isNonImmUse(N1.Val, N10.Val))) &&
       ...)

TableGen knows N1 must have more than one operand.

llvm-svn: 26592
 2006-03-07 08:31:27 +00:00
Chris Lattner
a31ef8a613 Silence a warning. 
llvm-svn: 26508
 2006-03-03 19:34:28 +00:00
Chris Lattner
d2068344fc Fix pasteo 
llvm-svn: 26499
 2006-03-03 06:13:41 +00:00
Chris Lattner
c8db4dd179 remove a bunch of long-dead testing code 
llvm-svn: 26497
 2006-03-03 02:34:28 +00:00
Chris Lattner
0b3c1c1fe2 initial implementation of intrinsic parsing 
llvm-svn: 26495
 2006-03-03 02:32:46 +00:00
Chris Lattner
b878804a5f remove out of date comment 
llvm-svn: 26492
 2006-03-03 02:04:07 +00:00
Chris Lattner
29d28e02b0 Add support for "-Ifoo" in addition to "-I foo" 
llvm-svn: 26487
 2006-03-03 01:53:40 +00:00
Chris Lattner
90eecf3882 Regenerate 
llvm-svn: 26486
 2006-03-03 01:47:37 +00:00
Chris Lattner
10c2fb116d add support for multiple include directories 
llvm-svn: 26485
 2006-03-03 01:47:14 +00:00
Evan Cheng
9539ab3ecc New vector type v2f32. 
llvm-svn: 26437
 2006-03-01 01:10:52 +00:00
Chris Lattner
1ffa8d3666 Select inline asm memory operands. 
llvm-svn: 26349
 2006-02-24 02:13:31 +00:00
Evan Cheng
6a9422ce1c Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit 
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294
 2006-02-20 22:34:53 +00:00
Jeff Cohen
6e4fbcce8f Fix bugs identified by VC++. 
llvm-svn: 26287
 2006-02-18 03:20:33 +00:00
Evan Cheng
110f651cba Bump up pattern cost if the resulting instruction is marked 
usesCustomDAGSchedInserter.

llvm-svn: 26282
 2006-02-18 02:33:09 +00:00
Chris Lattner
0974ebab7b Check the new form for bison output into CVS 
llvm-svn: 26208
 2006-02-15 07:24:01 +00:00
Chris Lattner
be28034223 Adjust to new form of handling lexer dependencies, this way shouldn't have 
the problems the old way did.

llvm-svn: 26161
 2006-02-14 05:13:13 +00:00
Evan Cheng
e8a0e56482 Call InsertISelMapEntry rather than map insertion operator to prevent overly 
aggrssive inlining. This reduces Select_store frame size from 24k to 10k.

llvm-svn: 26095
 2006-02-09 22:12:27 +00:00
Evan Cheng
fd9315eaaa Match getTargetNode() changes (now returns SDNode* instead of SDOperand). 
llvm-svn: 26084
 2006-02-09 07:16:09 +00:00
Evan Cheng
521e5a1bfe Change Select() from 
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);

llvm-svn: 26067
 2006-02-09 00:37:58 +00:00
Evan Cheng
0ff5d88abd Hoist all SDOperand declarations within a Select_{opcode}() to the top level 
to reduce stack memory usage. This is intended to work around the gcc bug.

llvm-svn: 26026
 2006-02-07 00:37:41 +00:00
Chris Lattner
cf81cdcf95 Add support for modifier strings in machine instr descriptions. This allows 
us to avoid creating lots of "Operand" types with different printers, instead
we can fold several together and use modifiers.  For example, we can now use:

${target:call} to say that the operand should be printed like a 'call' operand.

llvm-svn: 26024
 2006-02-06 23:40:48 +00:00
Chris Lattner
232dd5c069 Simplify the variant handling code, no functionality change. 
llvm-svn: 26023
 2006-02-06 22:43:28 +00:00
Evan Cheng
2af9230f1e At the end of isel, select a replacement node for each handle that does not 
have one. This can happen if a load's real uses are dead (i.e. they do not
have uses themselves).

llvm-svn: 26014
 2006-02-06 08:12:55 +00:00
Evan Cheng
6f1778d4e1 Name change. 
llvm-svn: 26013
 2006-02-06 06:03:35 +00:00
Evan Cheng
09b5e544a9 Handle HANDLENODE: just return itself. 
llvm-svn: 26011
 2006-02-05 08:46:14 +00:00
Evan Cheng
0b5d4a10a9 Allow more loads to be folded which were previously prevented from happening 
due to ordering issue. i.e. they were selected for chain use first.
Now at load select time, check if it is being selected for a chain use and if
it has only a single real use. If so, return a HANDLENODE (with the load as
its operand) in its place and record it.
When it is folded or the load is selected for a real use, the isel records it
as the replacement for the HANDLENODE. The replacement is done when all nodes
are selected.
This scheme exposed a couple of problems where cycles can happen. (See comments
in EmitMatchCode() for descriptions of the problems and their workaround /
solutions.) These problems have been resolved with a small compile time
penality.

llvm-svn: 25995
 2006-02-05 06:43:12 +00:00
Evan Cheng
d5d3d7ad9e Re-committing the last bit of change. It shouldn't break PPC this time. 
llvm-svn: 25982
 2006-02-05 05:22:18 +00:00
Chris Lattner
951217976d Temporarily revert the last change, which breaks PPC and other targets that 
DO select things.

llvm-svn: 25970
 2006-02-04 09:23:06 +00:00
Evan Cheng
6a366c5eda Complex pattern's custom matcher should not call Select() on any operands. 
Select them afterwards if it returns true.

llvm-svn: 25968
 2006-02-04 08:50:49 +00:00
Chris Lattner
21f305febf node predicates add to the complexity of a pattern. This ensures that the 
X86 backend attempts to match small-immediate versions of instructions before
the full size immediate versions.

llvm-svn: 25937
 2006-02-03 18:06:02 +00:00
Evan Cheng
7c8bab62e5 (store (op (load ...))) folding problem. In the generated matching code, 
Chain is initially set to the chain operand of store node, when it reaches
load, if it matches the load then Chain is set to the chain operand of the
load.

However, if the matching code that follows this fails, isel moves on to the
next pattern but it does not restore Chain to the chain operand of the store.
So when it tries to match the next store / op / load pattern it would fail on
the Chain == load.getOperand(0) test.

The solution is for each chain operand to get a unique name. e.g. Chain10.

llvm-svn: 25931
 2006-02-03 06:22:41 +00:00
Chris Lattner
c9a001a67d add a note, ya knoe 
llvm-svn: 25880
 2006-02-01 19:12:23 +00:00
Evan Cheng
efdfb534a7 If a pattern's root node is a constant, its size should be 3 rather than 2. 
llvm-svn: 25870
 2006-02-01 06:06:31 +00:00
Chris Lattner
8d9da62be7 implement test/Regression/TableGen/DagIntSubst.ll 
llvm-svn: 25836
 2006-01-31 06:02:35 +00:00
Chris Lattner
b7616b85bc simplify some code 
llvm-svn: 25791
 2006-01-29 20:01:35 +00:00
Andrew Lenharth
1ba3cfd622 it is nice not to chop off bits for those blessed with lots of bits 
llvm-svn: 25766
 2006-01-29 05:22:37 +00:00
Andrew Lenharth
fde505e9f5 make the casts actually cast to the variable type 
llvm-svn: 25765
 2006-01-29 05:17:22 +00:00
Andrew Lenharth
896015b24f start of the 64bit safety cleanup 
llvm-svn: 25764
 2006-01-29 05:07:04 +00:00
Chris Lattner
024ea8e7ca Emit series of conditionals with &&, emitting stuff like this: 
if (N1.getOpcode() == ISD::LOAD &&
        N1.hasOneUse() &&
        !CodeGenMap.count(N1.getValue(0)) &&
        !CodeGenMap.count(N1.getValue(1))) {

instead of this:

    if (N1.getOpcode() == ISD::LOAD) {
      if (N1.hasOneUse()) {
        if (!CodeGenMap.count(N1.getValue(0))) {
          if (!CodeGenMap.count(N1.getValue(1))) {

llvm-svn: 25763
 2006-01-29 04:41:05 +00:00
Chris Lattner
8624868903 Factor matching code that is common between patterns. This works around 
GCC not jump-threading across this common code, and produces far nicer
output.

llvm-svn: 25762
 2006-01-29 04:25:26 +00:00
Chris Lattner
f94049edf9 Split out code generation from analysis from emission 
llvm-svn: 25759
 2006-01-29 02:57:39 +00:00
Chris Lattner
6be3b584f4 move some code around, no change in the generated code 
llvm-svn: 25758
 2006-01-29 02:43:35 +00:00
Chris Lattner
3cdfba635c now that we have control over emission of the code, emit the code using nested 
"if" statements (indenting it appropriately, of course) instead of using goto's.

This inverts the logic for all of the if statements, which makes things simpler
to understand in addition to making the generated code easier to read.

llvm-svn: 25757
 2006-01-28 20:43:52 +00:00
Chris Lattner
b6fc7b5e71 Change PatternCodeEmitter to emit code into a buffer instead of emitting it 
directly to the output file.  This makes things simple because the code doesn't
have to worry about indentation or the case when there is no goto.  It also
allows us to indent the code better without touching everything :)

llvm-svn: 25756
 2006-01-28 20:31:24 +00:00
Chris Lattner
d9026d62f8 Fit to 80 columns, no functionality change 
llvm-svn: 25752
 2006-01-28 19:06:51 +00:00
Jeff Cohen
96bb922537 Teach tablegen to generate code that is VC++ warning-free. 
llvm-svn: 25709
 2006-01-27 22:22:28 +00:00
Evan Cheng
450fcb1d91 (store (op (load ...)), ...) 
If store's chain operand is load, then use load's chain operand instead. If
it isn't (likely a TokenFactor), then do not allow the folding.

llvm-svn: 25708
 2006-01-27 22:13:45 +00:00
Evan Cheng
77885c204d Subtarget feature can now set any variable to any value 
llvm-svn: 25678
 2006-01-27 08:09:42 +00:00
Chris Lattner
df97630390 Use printInlineAsm to, well, print inline asm's. 
llvm-svn: 25677
 2006-01-27 02:10:50 +00:00
Chris Lattner
cc5d4e56f0 PHI and INLINEASM are now builtin instructions provided by Target.td 
llvm-svn: 25673
 2006-01-27 01:45:06 +00:00
Chris Lattner
c3d295a47c If we want to emit things in enum order, use getInstructionsByEnumValue to 
get the order, don't compute it ourselves.

Don't emit stuff like (14<<0), emit 14 instead.

Don't attempt to get target properties for builtin instructions.

llvm-svn: 25672
 2006-01-27 01:44:09 +00:00
Chris Lattner
a932c5aafb There is at least a 'noitinerary' itinerary now 
llvm-svn: 25671
 2006-01-27 01:41:55 +00:00
Chris Lattner
1ec0a10fed Don't emit JIT code for these instructions 
llvm-svn: 25669
 2006-01-27 01:39:38 +00:00
Chris Lattner
0ee2c3b109 Teach the dag selectors to select InlineAsm nodes. 
Aren't we happy the pattern selectors are almost all gone?

llvm-svn: 25666
 2006-01-26 23:08:55 +00:00
Evan Cheng
8b6fb0763c Another folding problem: if a node r/w chain or flag, don't fold it if it 
has already been selected. The number of use check is not strong enough since
a node can be replaced with newly created target node. e.g. If the original
node has two uses, when it is selected for one of the uses it is replaced with
another. Each node now has a single use but isel still should not fold it.

llvm-svn: 25651
 2006-01-26 19:13:45 +00:00
Evan Cheng
37d647c562 Add a FIXME comment. 
llvm-svn: 25635
 2006-01-26 02:13:31 +00:00
Evan Cheng
849d522805 Incoming (and optional) flag bugs. They may be embedded inside a inner node of 
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.

llvm-svn: 25627
 2006-01-26 00:22:25 +00:00
Evan Cheng
dd2ee4821a Fix an optional in flag bug. 
llvm-svn: 25590
 2006-01-24 20:46:50 +00:00
Evan Cheng
1f68845c8c Optional InFlag was not being included in node. 
llvm-svn: 25588
 2006-01-24 20:07:38 +00:00
Evan Cheng
d3713a9b9a Prevent folding of a node with multiple uses if the node already folds a load! 
Here is an example where the load ended up being done twice:

%A = global uint 0

uint %test(uint %B, ubyte %C) {
	%tmp = load uint *%A;
	%X = shl uint %tmp, ubyte %C
	%Cv = sub ubyte 32, %C
	%Y = shr uint %B, ubyte %Cv
	%Z = or uint %Y, %X
	store uint %Z, uint* %A
	ret uint %Z
}

==>

	subl $4, %esp
	movl %ebx, (%esp)
	movl 8(%esp), %edx
	movl A, %eax
	movb 12(%esp), %bl
	movb %bl, %cl
	shldl %cl, %edx, %eax
	movb %bl, %cl
	shldl %cl, %edx, A
	movl (%esp), %ebx
	addl $4, %esp
	ret

llvm-svn: 25471
 2006-01-20 01:11:03 +00:00
Evan Cheng
4a3ee9d5a6 Bug fix. Flag operand number may be calculated incorrectly. 
llvm-svn: 25465
 2006-01-19 21:57:10 +00:00
Evan Cheng
f168c680e5 Use pattern information to determine whether the use expects this 
instruction to produce a result. e.g MUL8m, the instruction does not
produce a explicit result. However it produces an implicit result in
AL which would be copied to a temp. The root operator of the matching
pattern is a mul so the use would expect it to produce a result.

llvm-svn: 25458
 2006-01-19 10:12:58 +00:00
Evan Cheng
49fa8f2cea Prevent unnecessary CopyToReg when the same HW register appears in two spots 
in the pattern.

llvm-svn: 25437
 2006-01-19 01:55:45 +00:00
Chris Lattner
6efb726290 fix a broken comment 
llvm-svn: 25411
 2006-01-17 21:31:18 +00:00
John Criswell
ab12f83120 Regenerated the Lex and Yacc output files on Linux. It seems that our 
Linux machines don't like the source code generated on MacOS X for some
reason.

llvm-svn: 25394
 2006-01-17 17:01:34 +00:00
Evan Cheng
e840301269 Emit a type matching check for ComplexPatterns. 
llvm-svn: 25392
 2006-01-17 07:36:41 +00:00
Evan Cheng
ddc62a9b61 Type inferencing bug 
llvm-svn: 25337
 2006-01-15 10:04:45 +00:00
Evan Cheng
dc7ec6c63e Allow transformation from GlobalAddress to TargetGlobalAddress and 
ExternalSymbol to TargetExternalSymbol.

llvm-svn: 25252
 2006-01-12 19:35:54 +00:00
Evan Cheng
bbe910088d GlobalAddress -> TargetGlobalAddress; ExternalSymbol -> TargetExternalSymbol 
llvm-svn: 25245
 2006-01-12 07:54:57 +00:00
Evan Cheng
5fa1397b29 Some minor fixes. 
llvm-svn: 25227
 2006-01-11 22:16:13 +00:00
Chris Lattner
4e465047c1 Always select target registers to themselves 
llvm-svn: 25218
 2006-01-11 19:52:27 +00:00
Chris Lattner
0343518492 Emit an error instead of an assertion if trying to do bogus things in result patterns. 
llvm-svn: 25194
 2006-01-11 01:33:49 +00:00
Robert Bocchino
9a57550e4e Added support for the extractelement operation. 
llvm-svn: 25181
 2006-01-10 19:05:34 +00:00
Evan Cheng
7b8f8c317e * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and 
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.

llvm-svn: 25154
 2006-01-09 18:27:06 +00:00
Evan Cheng
353958d60c Pattern complexity calculation fix. 
llvm-svn: 25133
 2006-01-06 22:19:44 +00:00
Evan Cheng
1d376c6eb2 Tweak pattern complexity calc. 
llvm-svn: 25122
 2006-01-06 02:30:23 +00:00
Evan Cheng
c6ad7a02a8 Bug fix wrt chain operand. 
llvm-svn: 25115
 2006-01-06 00:41:12 +00:00
Jeff Cohen
2230844c7b Replace fix with one less disruptive to the original code. 
Also note that GCC 4.1 also correctly flags the syntax error.

llvm-svn: 25076
 2006-01-04 03:23:30 +00:00
Jeff Cohen
8c5173a440 Tblgen was generating syntactically illegal C++ code like: 
SDOperand Tmp0,Tmp1,Tmp2,Tmp3,;

GCC has a bug (24907) in which is fails to catch this, but VC++ correctly
notes its illegality, so tblgen must be taught to only generate legal C++.

llvm-svn: 25075
 2006-01-04 03:15:19 +00:00
Chris Lattner
5a6761490a Remove obsolete comment, make things look a bit nicer 
llvm-svn: 25070
 2006-01-04 00:32:01 +00:00
Chris Lattner
ae035f3604 reduce stack usage of the recursive SelectCode function by out-lining each 
case of the switch statement into its own method.

llvm-svn: 25069
 2006-01-04 00:25:00 +00:00
Chris Lattner
f6418363ba Remove my previous ugly hack that tries to reduce the stack space usage 
of SelectCode to make way for a better solution.

llvm-svn: 25068
 2006-01-03 22:55:16 +00:00
Duraid Madina
d3cf232a4f HP-UX DVDs are crunchy and good to eat 
llvm-svn: 25052
 2005-12-30 16:41:48 +00:00
Duraid Madina
c4a1bfd13d almost got the HP-UX tester up.. :) 
llvm-svn: 25051
 2005-12-30 14:56:37 +00:00
Nate Begeman
ec7c28a28c Add support for generating v4i32 altivec code 
llvm-svn: 25046
 2005-12-30 00:12:56 +00:00
Duraid Madina
d63b3a13cc This gets most of the backends building with HP HappyC++. 
llvm-svn: 25029
 2005-12-27 10:56:22 +00:00
Evan Cheng
231b11ba87 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Duraid Madina
b8be651393 more standards-compliance stuff 
llvm-svn: 25014
 2005-12-26 05:08:55 +00:00
Andrew Lenharth
b42cc57048 support targetexternalsym 
llvm-svn: 25005
 2005-12-24 23:36:59 +00:00
Evan Cheng
bd79f871a2 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG 
support which is fragile.
* Fixed a number of bugs.

llvm-svn: 24996
 2005-12-23 22:11:47 +00:00
Chris Lattner
d752db6276 silence some bogus gcc warnings 
llvm-svn: 24962
 2005-12-22 20:37:36 +00:00
Evan Cheng
b18b8c847f Attempt to fix a crash on WIN32. 
llvm-svn: 24936
 2005-12-22 02:35:21 +00:00
Evan Cheng
578fad3f9d * Added support for FLAG - a special nameless flag register. Can be used as 
either an operand or a result.
* Fixed some more flag / chain bugs.

llvm-svn: 24933
 2005-12-22 02:24:50 +00:00
Evan Cheng
3b09247bb9 Allows instructions which no explicit operands. e.g. X86 RET which has but 
an implicit flag operand.

llvm-svn: 24916
 2005-12-21 20:20:49 +00:00
Chris Lattner
643e6c2b9e Eliminate some GCC warnings from the generated code 
llvm-svn: 24897
 2005-12-21 05:31:05 +00:00
Evan Cheng
4106feae54 Fix the semantic of Requires<[cond]> to mean if (!cond) goto PXXFail; 
llvm-svn: 24883
 2005-12-20 20:08:01 +00:00
Chris Lattner
28cf136707 This ugly patch works around a GCC bug where it is compiling SelectCode to 
use too much stack space, overflowing the stack for large functions.  Instead
of emitting new SDOperands in each match block, we emit some common ones at
the top of SelectCode then reuse them when possible.

This reduces the stack size of SelectCode from 28K to 21K.  Note that GCC
compiles it to 512 bytes :-/

I've filed GCC PR 25505 to track this.

llvm-svn: 24882
 2005-12-20 19:41:03 +00:00
Evan Cheng
98c6b52236 Now support instructions with implicit write to non-flag registers. 
llvm-svn: 24878
 2005-12-20 07:37:41 +00:00
Evan Cheng
63d897b0e2 Lefted out a fix in the previous check in. 
llvm-svn: 24873
 2005-12-20 00:06:17 +00:00
Evan Cheng
e93635d0ac Fix another bug related to chain / flag. 
llvm-svn: 24868
 2005-12-19 22:40:04 +00:00
Evan Cheng
c56f9824db Fixes for a number of bugs: save flag results in CodeGenMap, folded chains 
may not all have ResNo == 0.

llvm-svn: 24858
 2005-12-19 07:18:51 +00:00
Chris Lattner
abadc27396 Handle basic block nodes 
llvm-svn: 24833
 2005-12-18 21:05:44 +00:00
Chris Lattner
5dfbcbb8be More fixes for Selection of copyto/fromreg with a flag 
llvm-svn: 24829
 2005-12-18 15:45:51 +00:00
Chris Lattner
5322894560 Select copytoreg and copyfromreg nodes that have flag operands correctly. 
llvm-svn: 24827
 2005-12-18 15:28:25 +00:00
Evan Cheng
54695fd38d Support for read / write from explicit registers with FlagVT type. 
llvm-svn: 24753
 2005-12-17 01:19:28 +00:00
Evan Cheng
297c23d2e7 Added support to specify predicates. 
llvm-svn: 24715
 2005-12-14 22:02:59 +00:00
Evan Cheng
81f4683257 Skip over srcvalue nodes when generating ISEL code. 
llvm-svn: 24704
 2005-12-14 02:21:57 +00:00
Evan Cheng
518610154b Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ... 
llvm-svn: 24680
 2005-12-12 23:45:21 +00:00
Evan Cheng
1bc6443c22 At top of generated isel SelectCode() is this: 
if (!N.Val->hasOneUse()) {
    std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
    if (CGMI != CodeGenMap.end()) return CGMI->second;
  }

Suppose a DAG like this:

           X
         ^   ^
        /     \
      USE1    USE2

Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!

The fix is to always query CodeGenMap.

llvm-svn: 24679
 2005-12-12 23:22:48 +00:00
Evan Cheng
e7f40a3b8b Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible. 
llvm-svn: 24669
 2005-12-12 19:37:43 +00:00
Nate Begeman
a0e26b25f4 Add support for TargetConstantPool nodes to the dag isel emitter, and use 
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.

llvm-svn: 24657
 2005-12-10 02:36:00 +00:00
Evan Cheng
c8ebe5f6eb Stop emitting a redudant type check for complex pattern node. 
llvm-svn: 24655
 2005-12-10 01:57:33 +00:00
Evan Cheng
8300ae66d1 For instructions which produce no result, e.g. store, chain's Resno == 0. 
llvm-svn: 24652
 2005-12-10 00:09:17 +00:00
Chris Lattner
aaec1f6faa Add a new SDTCisPtrTy constraint, which indicates that an operand must have 
the same type as the pointer type for a target.

llvm-svn: 24649
 2005-12-09 22:57:42 +00:00
Evan Cheng
9586e87904 * Do not allow nodes which produce chain results (e.g. loads) to be folded if 
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
  operand of a chain use.

llvm-svn: 24647
 2005-12-09 22:45:35 +00:00
Evan Cheng
18134d8c96 Prevent folding of instructions which produce chains that have more than 1 real use 
llvm-svn: 24643
 2005-12-09 06:06:08 +00:00
Evan Cheng
1d7435f478 * Make sure complex pattern operands are selected first since their select 
functions can return false and causing the instruction pattern match to fail.
* Code clean up.

llvm-svn: 24642
 2005-12-09 00:48:42 +00:00
Evan Cheng
ed205f20a5 * Added an explicit type field to ComplexPattern. 
* Renamed MatchingNodes to RootNodes.

llvm-svn: 24636
 2005-12-08 02:14:08 +00:00
Evan Cheng
d11d31e0bd Added support for ComplexPattern. These are patterns that require C++ pattern 
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.

llvm-svn: 24634
 2005-12-08 02:00:36 +00:00
Evan Cheng
3d51fa3305 * Infer instruction property hasCtrlDep from pattern if it has one. 
* Fixed a bug related to hasCtrlDep property use.

llvm-svn: 24610
 2005-12-05 23:08:55 +00:00
Chris Lattner
8ef7c0297c Implement PR673: for explicit register references, use type information 
if available

llvm-svn: 24597
 2005-12-05 02:36:37 +00:00