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Commit Graph

125831 Commits

Author SHA1 Message Date
Evgeniy Stepanov
768d8b571a MemTag: stack initializer merging.
Summary:
MTE provides instructions to update memory tags and data at the same
time. This change makes use of those to generate more compact code for
stack variable tagging + initialization.

We collect memory store and memset instructions following an alloca or a
lifetime.start call, and replace them with the corresponding MTE
intrinsics. Since the intrinsics work on 16-byte aligned chunks, the
stored values are combined as necessary.

Reviewers: pcc, vitalybuka, ostannard

Subscribers: srhines, javed.absar, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66167

llvm-svn: 369297
2019-08-19 20:47:09 +00:00
Benjamin Kramer
39257e2226 [Support] Replace sys::Mutex with their standard equivalents.
Only use a recursive mutex if it can be locked recursively.

llvm-svn: 369295
2019-08-19 19:49:57 +00:00
Johannes Doerfert
f1df01d3ad Re-apply fixed "[Attributor] Fix: Make sure we set the changed flag"
This reverts commit cedd0d9a6e4b433e1cd6585d1d4d152eb5e60b11.

Re-apply the original commit but make sure the variables are initialized
(even if they are not used) so UBSan is not complaining.

llvm-svn: 369294
2019-08-19 19:14:10 +00:00
Sam Clegg
39e2f92942 [WebAssembly][MC] Allow empty assembly functions
Differential Revision: https://reviews.llvm.org/D66434

llvm-svn: 369292
2019-08-19 19:04:54 +00:00
Alina Sbirlea
5d82ced509 [MemorySSA] Rename uses when inserting memory uses.
Summary:
When inserting uses from outside the MemorySSA creation, we don't
normally need to rename uses, based on the assumption that there will be
no inserted Phis (if  Def existed that required a Phi, that Phi already
exists). However, when dealing with unreachable blocks, MemorySSA will
optimize away Phis whose incoming blocks are unreachable, and these Phis end
up being re-added when inserting a Use.
There are two potential solutions here:
1. Analyze the inserted Phis and clean them up if they are unneeded
(current method for cleaning up trivial phis does not cover this)
2. Leave the Phi in place and rename uses, the same way as whe inserting
defs.
This patch use approach 2.

Resolves first test in PR42940.

Reviewers: george.burgess.iv

Subscribers: Prazek, sanjoy.google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66033

llvm-svn: 369291
2019-08-19 18:57:40 +00:00
Craig Topper
531e6f449d [X86] Teach lowerV4I32Shuffle to only use broadcasts if the mask has more than one undef element. Prioritize shifts over broadcast in lowerV8I16Shuffle.
The motivating case are the changes in vector-reduce-add.ll where
we were doing extra work in the scalar domain instead of shuffling.
There may be some one use check that needs to be looked into there,
but this patch sidesteps the issue by avoiding broadcasts that
aren't really broadcasting.

Differential Revision: https://reviews.llvm.org/D66071

llvm-svn: 369287
2019-08-19 18:15:50 +00:00
Craig Topper
4054fdb457 [CGP] Remove ModifiedDT from the makeBitReverse loop
I don't think anything in this loop modifies the control flow and we don't restart any iteration after setting the flag.

This code was added in http://reviews.llvm.org/D16893 but looking at the test case added there the code that caused the dominator tree to change was merging blocks with their predecessor not the bitreverse optimization.

Differential Revision: https://reviews.llvm.org/D66366

llvm-svn: 369283
2019-08-19 18:02:24 +00:00
Pavel Labath
5c31a20ba7 Filesystem/Windows: fix inconsistency in readNativeFileSlice API
Summary:
The windows version implementation of readNativeFileSlice, was trying to
match the POSIX behavior of not treating EOF as an error, but it was
only handling the case of reading from a pipe. Attempting to read past
the end of a regular file returns a slightly different error code, which
needs to be handled too. This patch adds ERROR_HANDLE_EOF to the list of
error codes to be treated as an end of file, and adds some unit tests
for the API.

This issue was found while attempting to land D66224, which caused a bunch of
lldb tests to start failing on windows.

Reviewers: rnk, aganea

Subscribers: kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66344

llvm-svn: 369269
2019-08-19 15:40:49 +00:00
Roman Lebedev
120ce0f066 [TargetLowering] x s% C == 0 fold: vector divisor with INT_MIN handling
Summary:
The general fold is only valid for positive divisors.
Which effectively means, it is invalid for `INT_MIN` divisors,
and we currently bailout if we see them.

But that is too strict, we can just fix-up the results.
For that, let's do a second computation 'in parallel':
```
Name: srem -> and
Pre: isPowerOf2(C)
%o = srem i8 %X, C
%r = icmp eq %o, 0
  =>
%n = and i8 %X, C-1
%r = icmp eq %n, 0
```
https://rise4fun.com/Alive/Sup

And then just blend results: if the divisor was `INT_MIN`,
pick the value we got via bit-test,
else pick the value from general fold.

There's interesting observation - `ISD::ROTR` is set to
`LegalizeAction::Expand` before AVX512, so we should not
treat `INT_MIN` divisor as even; and as it can be seen
while `@test_srem_odd_even_one` improves on all run-lines,
`@test_srem_odd_even_INT_MIN` only improves for AVX512.

Reviewers: RKSimon, craig.topper, spatel

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66300

llvm-svn: 369268
2019-08-19 15:01:42 +00:00
Serge Guelton
d9db87717d [nfc] Silent gcc warning
llvm-svn: 369266
2019-08-19 14:40:33 +00:00
George Rimar
4603392e6d [Object/COFF.h] - Stop returning std::error_code in a few methods. NFCI.
There are 4 methods that return std::error_code now,
though they do not have to because they are always succeed.
I refactored them.

This allows to simplify the code in tools a bit.

llvm-svn: 369263
2019-08-19 14:32:23 +00:00
Jinsong Ji
af77a2caf6 [PeepholeOptimizer] Don't assume bitcast def always has input
Summary:
If we have a MI marked with bitcast bits, but without input operands,
PeepholeOptimizer might crash with assert.

eg:
If we apply the changes in PPCInstrVSX.td as in this patch:

[(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>;

We will get assert in PeepholeOptimizer.

```
llvm-lit llvm-project/llvm/test/CodeGen/PowerPC/build-vector-tests.ll -v

llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h:417: const
llvm::MachineOperand &llvm::MachineInstr::getOperand(unsigned int)
const: Assertion `i < getNumOperands() && "getOperand() out of range!"'
failed.
```

The fix is to abort if we found out of bound access.

Reviewers: qcolombet, MatzeB, hfinkel, arsenm

Reviewed By: qcolombet

Subscribers: wdng, arsenm, steven.zhang, wuzish, nemanjai, hiraditya, kbarton, MaskRay, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65542

llvm-svn: 369261
2019-08-19 14:19:04 +00:00
Alex Bradbury
6f3092d9ba [RISCV] Don't force absolute FK_Data_X fixups to relocs
The current behavior of shouldForceRelocation forces relocations for the
majority of fixups when relaxation is enabled. This makes sense for
fixups which incorporate symbols but is unnecessary for simple data
fixups where the fixup target is already resolved to an absolute value.

Differential Revision: https://reviews.llvm.org/D63404
Patch by Edward Jones.

llvm-svn: 369257
2019-08-19 13:23:02 +00:00
David Stenberg
1579e1dd64 [DebugInfo] Allow bundled calls in the MIR's call site info
Summary:
Extend the MIR parser and writer so that the call site information can
refer to calls that are bundled.

Reviewers: aprantl, asowda, NikolaPrica, djtodoro, ivanbaev, vsk

Reviewed By: aprantl

Subscribers: arsenm, hiraditya, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D66145

llvm-svn: 369256
2019-08-19 12:41:22 +00:00
Sanjay Patel
dfce324623 [SLP] reduce duplicated code; NFC
llvm-svn: 369250
2019-08-19 11:39:56 +00:00
Fangrui Song
d7fb689cc7 [MC] Simplify ELFObjectWriter::recordRelocation. NFC
llvm-svn: 369248
2019-08-19 10:05:59 +00:00
Jeremy Morse
0dad0e2b4e [DebugInfo] Make postra sinking of DBG_VALUEs subregister-safe
Currently the machine instruction sinker identifies DBG_VALUE insts that
also need to sink by comparing register numbers. Unfortunately this isn't
safe, because (after register allocation) a DBG_VALUE may read a register
that aliases what's being sunk. To fix this, identify the DBG_VALUEs that
need to sink by recording & examining their register units. Register units
gives us the following guarantee:

  "Two registers overlap if and only if they have a common register unit"
  [MCRegisterInfo.h]

Thus we can always identify aliasing DBG_VALUEs if the set of register
units read by the DBG_VALUE, and the register units of the instruction
being sunk, intersect. (MachineSink already uses classes like
"LiveRegUnits" for determining sinking validity anyway).

The test added checks for super and subregister DBG_VALUE reads of a sunk
copy being sunk as well.

Differential Revision: https://reviews.llvm.org/D58191

llvm-svn: 369247
2019-08-19 09:53:07 +00:00
Sam Tebbs
11317955ae [ARM] Add support for MVE vaddv
This patch adds vecreduce_add and the relevant instruction selection for
vaddv.

Differential revision: https://reviews.llvm.org/D66085

llvm-svn: 369245
2019-08-19 09:38:28 +00:00
David Green
589db557e7 [ARM] MVE sext costs
This adds some sext costs for MVE, taken from the length of assembly sequences
that we currently generate.

Differential Revision: https://reviews.llvm.org/D66010

llvm-svn: 369244
2019-08-19 09:13:22 +00:00
David L. Jones
c75f9e4407 Revert [Attributor] Fix: Make sure we set the changed flag
This reverts r369159 (git commit cbaf1fdea2de891bdbc49cdec89ae2077e6b9ed0)

r369160 caused a test to fail under UBSAN. See thread on llvm-commits.

llvm-svn: 369241
2019-08-19 08:00:08 +00:00
Fangrui Song
73a8f9248f [MC] Delete unnecessary diagnostic: "No relocation available to represent this relative expression"
Replace

- error: No relocation available to represent this relative expression

with

+ error: symbol 'undef' can not be undefined in a subtraction expression

or

+ error: Cannot represent a difference across sections

Keep !IsPcRel as an assertion after the two diagnostic checks are done.

llvm-svn: 369239
2019-08-19 07:59:35 +00:00
David L. Jones
dbac100350 Revert [Attributor] Fix: Do not partially resolve returned calls.
This reverts r369160 (git commit f72d9b1c97b41fff48ad1eecbba59a29c171bff4)

r369160 caused some tests to fail under UBSAN. See thread on llvm-commits.

llvm-svn: 369236
2019-08-19 07:16:24 +00:00
Fangrui Song
d2dba26b00 [MC] Don't emit .symver redirected symbols to the symbol table
GNU as keeps the original symbol in the symbol table for defined @ and
@@, but suppresses it in other cases (@@@ or undefined). The original
symbol is usually undesired:
In a shared object, the original symbol can be localized with a version
script, but it is hard to remove/localize in an archive:

1) a post-processing step removes the undesired original symbol
2) consumers (executable) of the archive are built with the
   version script

Moreover, it can cause linker issues like binutils PR/18703 if the
original symbol name and the base name of the versioned symbol is the
same (both ld.bfd and gold have some code to work around defined @ and
@@). In lld, if it sees f and f@v1:

  --version-script =(printf 'v1 {};') => f and f@v1
  --version-script =(printf 'v1 { f; };') => f@v1 and f@@v1

It can be argued that @@@ added on 2000-11-13 corrected the @ and @@ mistake.

This patch catches some more multiple version errors (defined @ and @@),
and consistently suppress the original symbol. This addresses all the
problems listed above.

If the user wants other aliases to the versioned symbol, they can copy
the original symbol to other symbol names with .set directive, e.g.

    .symver f, f@v1  # emit f@v1 but not f into .symtab
    .set f_impl, f   # emit f_impl into .symtab

llvm-svn: 369233
2019-08-19 06:17:30 +00:00
Craig Topper
e6284d6256 [X86] Teach lower1BitShuffle to match right shifts with upper zero elements on types that don't natively support KSHIFT.
We can support these by widening to a supported type,
then shifting all the way to the left and then
back to the right to ensure that we shift in zeroes.

llvm-svn: 369232
2019-08-19 05:45:39 +00:00
Craig Topper
b738257b1e [X86] Fix the lower1BitShuffle code added in r369215 to correctly pass the widened vector to the KSHIFT node.
Not sure how to test this as we have tests that exercise this code,
but nothing failed for the types not matching. Since all the k-registers
use equivalent register classes everything just ends up working.

llvm-svn: 369228
2019-08-19 04:08:44 +00:00
Craig Topper
6120ffd771 [X86] Teach lower1BitShuffle to match KSHIFTR that doesn't use Zeroable and only relies on undef.
This allows us to widen the type when the KSHIFTR instruction
doesn't exist for the type. If we need to shift in zeroes into
the upper elements we would need more work to guarantee zeroes
when widening.

llvm-svn: 369227
2019-08-19 04:08:40 +00:00
Craig Topper
d41f80432f [X86] Teach lower1BitShuffle to recognize padding a subvector with zeros with V2 as the source and V1 as the zero vector.
Shuffle canonicalization can swap the sources so the zero vector
might be V1 and the subvector that's being padded can be V2.

llvm-svn: 369226
2019-08-19 00:39:22 +00:00
Craig Topper
94e5e63de0 [X86] Add a special case to LowerCONCAT_VECTORSvXi1 to handle concatenating zero vectors followed by one non-zero vector followed by undef vectors.
For such a case we should only need a KSHIFTL, but we were
previously generating a KSHIFTL followed by a KSHIFTR because
we mistakenly believed we need to zero the undef elements.

llvm-svn: 369224
2019-08-18 23:30:11 +00:00
Craig Topper
56c689516a [X86] Replace uses of getZeroVector for vXi1 vectors with DAG.getConstant.
vXi1 vectors don't need special handling.

llvm-svn: 369222
2019-08-18 23:30:03 +00:00
Craig Topper
1a4b504a13 [X86] Improve lower1BitShuffle handling for KSHIFTL on narrow vectors.
We can insert the value into a larger legal type and shift that
by the desired amount.

llvm-svn: 369215
2019-08-18 18:52:46 +00:00
Simon Pilgrim
22ccc56aca Fix signed/unsigned comparison warning. NFCI.
llvm-svn: 369213
2019-08-18 17:26:30 +00:00
Simon Pilgrim
6cb9bb2b52 [X86] isTargetShuffleEquivalent - add BUILD_VECTOR matching
Add similar functionality to isShuffleEquivalent - if the mask elements don't match, try matching the BUILD_VECTOR scalars instead.

As target shuffles need to handle SM_Sentinel values, this can get a bit tricky, so commit just adds actual mask element index handling - full SM_SentinelZero support will be added when the need arises.

Also, enables support in matchVectorShuffleWithPACK

llvm-svn: 369212
2019-08-18 17:15:26 +00:00
Simon Pilgrim
84c45fe64c [X86] isTargetShuffleEquivalent - early out on illegal shuffle masks. NFCI.
Simplifies shuffle mask comparisons by just bailing out if the shuffle mask has any out of range values - will make an upcoming patch much simpler.

llvm-svn: 369211
2019-08-18 16:37:58 +00:00
Roman Lebedev
a44ed33a51 [InstCombine] Cherry-pick NFC cleanups of foldShiftIntoShiftInAnotherHandOfAndInICmp() from D66383
llvm-svn: 369207
2019-08-18 12:26:33 +00:00
Craig Topper
70edb55508 [TargetLowering] Teach computeRegisterProperties to only widen v3i16/v3f16 vectors to the next power of 2 type if that's legal.
These were recently made simple types. This restores their
behavior back to something like their EVT legalization.

We might be able to fix the code in type legalization where the
assert was failing, but I didn't investigate too much as I had
already looked at the computeRegisterProperties code during the
review for v3i16/v3f16.

Most of the test changes restore the X86 codegen back to what
it looked like before the recent change. The test case in
vec_setcc.ll and is a reduced version of the reproducer from
the fuzzer.

Fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=16490

llvm-svn: 369205
2019-08-18 06:28:06 +00:00
Craig Topper
a41a47b2c1 [SelectionDAG] Add a node creation debug message to getMachineNode.
llvm-svn: 369204
2019-08-18 06:28:00 +00:00
Matt Arsenault
3d103cc66a AMDGPU: Fix iterator error when lowering SI_END_CF
If the instruction is the last in the block, there is no next
instruction but the iteration still needs to look at the new block.

llvm-svn: 369203
2019-08-18 00:20:44 +00:00
Matt Arsenault
7b3d83031a AMDGPU: Disambiguate v3f16 format in load/store tables
Currently the searchable tables report the number of dwords. These
round to the same number for 3 and 4 component d16
instructions. Change this to report the number of elements so this
isn't ambiguous.

llvm-svn: 369202
2019-08-18 00:20:43 +00:00
Craig Topper
77f3c2e9ff [X86] Add a one use check to the combineStore code that handles v16i16->v16i8 truncate+store by extending to v16i32 and then emitting a v16i32->v16i8 truncstore.
This prevent us from emitting a separate truncate and a truncating
store instruction.

llvm-svn: 369200
2019-08-17 22:46:15 +00:00
Yonghong Song
1e7c1b5239 [BPF] Fix bpf llvm-objdump issues.
Commit https://reviews.llvm.org/D57939 ("[DWARF] Refactor
RelocVisitor and fix computation of SHT_RELA-typed relocation entries)
made a change for relocation resolution when operating
on an object file.

The change unfortunately broke BPF as given SymbolValue (S) and
Addent (A), previously relocation is resolved to
    S + A
and after the change, it is resolved to
    S

This patch fixed the issue by resolving relocation correctly.

It looks not all relocation resolution reaches here and I did not
trace down exactly when. But I do find if the object file includes
codes in two different ELF sections than default ".text",
the above bug will be triggered.

This patch included a trivial two function source code to
demonstrate this issue. The relocation for .debug_loc is resolved
incorrectly due to this and llvm-objdump cannot display source
annotated assembly.

Differential Revision: https://reviews.llvm.org/D66372

llvm-svn: 369199
2019-08-17 22:12:00 +00:00
Kang Zhang
cd9e0c5c7a [CodeGen] Do the Simple Early Return in block-placement pass to optimize the blocks
Summary:

Fix a bug of preducessors.

In `block-placement` pass, it will create some patterns for unconditional we can do the simple early retrun.
But the `early-ret` pass is before `block-placement`, we don't want to run it again.
This patch is to do the simple early return to optimize the blocks at the last of `block-placement`.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D63972

llvm-svn: 369191
2019-08-17 14:37:05 +00:00
Paul Walker
699197ed9f Revert Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instructions.
This reverts r369132 (git commit 19301d75f086caae1a495d267f5d0264b225942d)

llvm-svn: 369186
2019-08-17 09:22:36 +00:00
Paul Walker
6baf63e72c Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instructions.
This reverts r369133 (git commit 2632c677f85cba1ac2aef5d68aaf8af0f5b3c944)

llvm-svn: 369185
2019-08-17 09:22:28 +00:00
Alina Sbirlea
738b9c0924 [MemorySSA] Loop passes should mark MSSA preserved when available.
This patch applies only to the new pass manager.
Currently, when MSSA Analysis is available, and pass to each loop pass, it will be preserved by that loop pass.
Hence, mark the analysis preserved based on that condition, vs the current `EnableMSSALoopDependency`. This leaves the global flag to affect only the entry point in the loop pass manager (in FunctionToLoopPassAdaptor).

llvm-svn: 369181
2019-08-17 01:02:12 +00:00
Sanjay Patel
808fb08483 Revert r367891 - "[InstCombine] combine mul+shl separated by zext"
This reverts commit 5dbb90bfe14ace30224239cac7c61a1422fa5144.

As noted in the post-commit thread for r367891, this can create
a multiply that is lowered to a libcall that may not exist.

We need to improve the backend decomposition for integer multiply
before trying to re-land this (if it's still worthwhile after
doing the backend work).

llvm-svn: 369174
2019-08-16 23:36:28 +00:00
Jian Cai
fa10d00255 Reland "[ARM] push LR before __gnu_mcount_nc"
This relands r369147 with fixes to unit tests.

https://reviews.llvm.org/D65019

llvm-svn: 369173
2019-08-16 23:30:16 +00:00
Amara Emerson
2d9a3e9605 [AArch64][GlobalISel] Fix an assertion during G_UNMERGE selection for s128 types.
llvm-svn: 369172
2019-08-16 23:23:40 +00:00
Sanjay Patel
45efa06f0f [CodeGenPrepare] Fix use-after-free
If OptimizeExtractBits() encountered a shift instruction with no operands at all,
it would erase the instruction, but still return false.

This previously didn’t matter because its caller would always return after
processing the instruction, but https://reviews.llvm.org/D63233 changed the
function’s caller to fall through if it returned false, which would then cause
a use-after-free detectable by ASAN.

This change makes OptimizeExtractBits return true if it removes a shift
instruction with no users, terminating processing of the instruction.

Patch by: @brentdax (Brent Royal-Gordon)

Differential Revision: https://reviews.llvm.org/D66330

llvm-svn: 369168
2019-08-16 23:10:34 +00:00
Jordan Rupprecht
3c8212e499 Revert [X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using DemandedElts mask (reapplied)
This reverts r368662 (git commit 1a8d790cf5f89c1df718844f13e934e39bef6ef5)

The compile-time regression repro is in https://bugs.llvm.org/show_bug.cgi?id=43024

llvm-svn: 369167
2019-08-16 23:08:56 +00:00
Eli Friedman
2e92bd613a [ARM] Preserve liveness in ARMConstantIslands.
We currently don't use liveness information after this point, but it can
be useful to catch bugs using -verify-machineinstrs, and optimizations
could potentially use this information in the future.

Differential Revision: https://reviews.llvm.org/D66319

llvm-svn: 369162
2019-08-16 22:20:14 +00:00