Evan Cheng
20086680b0
Don't put IT instruction before conditional branches.
...
llvm-svn: 75361
2009-07-11 07:26:20 +00:00
Evan Cheng
03d981d91b
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
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llvm-svn: 75360
2009-07-11 07:08:13 +00:00
Evan Cheng
268b47b1fb
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
...
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
Evan Cheng
e83b947a2c
80 col violation.
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llvm-svn: 75358
2009-07-11 06:37:27 +00:00
Bob Wilson
88593195a0
Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of
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quad registers and the Q4PR class holds sets of 4 quad registers.
llvm-svn: 75309
2009-07-10 23:09:06 +00:00
David Goodwin
1a6f4f6f8d
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
...
llvm-svn: 75254
2009-07-10 17:03:29 +00:00
David Goodwin
527180b7b0
t2LDM_RET does not fall-through.
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llvm-svn: 75250
2009-07-10 15:33:46 +00:00
Duncan Sands
eaa9975d59
Add Thumb2ITBlockPass.cpp to CMakeLists.txt, fixing
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the cmake build.
llvm-svn: 75246
2009-07-10 08:31:50 +00:00
Evan Cheng
6e276f4376
More info about Thumb1 predication support.
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llvm-svn: 75220
2009-07-10 02:10:17 +00:00
Evan Cheng
74f5327e53
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
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llvm-svn: 75219
2009-07-10 02:09:04 +00:00
Evan Cheng
24f2aefc87
Add a thumb2 pass to insert IT blocks.
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llvm-svn: 75218
2009-07-10 01:54:42 +00:00
Evan Cheng
4d2678d1ff
Move isPredicated from .cpp to .h
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llvm-svn: 75217
2009-07-10 01:38:27 +00:00
Evan Cheng
5bdb67db63
80 col violation.
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llvm-svn: 75212
2009-07-10 00:45:16 +00:00
Evan Cheng
4249ad4c00
Remove a bogus assertion.
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llvm-svn: 75206
2009-07-10 00:23:48 +00:00
Bob Wilson
3309c912fb
Replace TM.getRegisterInfo() calls by TRI instance variable.
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Use getAsmName() method instead of accessing AsmName field directly.
llvm-svn: 75205
2009-07-10 00:14:05 +00:00
Bob Wilson
f5f52fa9d6
Handle 'a' modifier on inline assembly operands.
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This is part of the fix for pr4521.
llvm-svn: 75201
2009-07-09 23:54:51 +00:00
Evan Cheng
1b15e9611e
Added Thumb IT instruction.
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llvm-svn: 75198
2009-07-09 23:43:36 +00:00
Evan Cheng
0d509459ff
Another todo entry.
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llvm-svn: 75192
2009-07-09 23:17:28 +00:00
Evan Cheng
5bde39cb50
Initial support for load / store multiple opt pass Thumb2 support (post-allocation only). It's kind of there, but not quite. I'll return to this later.
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llvm-svn: 75190
2009-07-09 23:11:34 +00:00
Evan Cheng
57a4e81f3f
Fix ldm / stm unified syntax; add t2LDM_RET.
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llvm-svn: 75188
2009-07-09 22:58:39 +00:00
Evan Cheng
09e7791563
LDM_RET should be marked mayLoad.
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llvm-svn: 75187
2009-07-09 22:57:41 +00:00
Evan Cheng
3b7c3fafab
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
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Note, we are not yet generating these instructions.
llvm-svn: 75181
2009-07-09 22:21:59 +00:00
Evan Cheng
7f8e728a54
Add a Thumb readme entry.
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llvm-svn: 75173
2009-07-09 20:50:52 +00:00
Evan Cheng
e08efed97a
Correct comment.
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llvm-svn: 75172
2009-07-09 20:40:44 +00:00
David Goodwin
6c4201dbcb
Handle Thumb-2 addressing modes during FP elimination.
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llvm-svn: 75158
2009-07-09 18:35:52 +00:00
Owen Anderson
8970999512
Thread LLVMContext through MVT and related parts of SDISel.
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llvm-svn: 75153
2009-07-09 17:57:24 +00:00
Evan Cheng
fad8f9bea1
Reorg includes.
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llvm-svn: 75115
2009-07-09 06:49:09 +00:00
David Goodwin
49fbd8d6b7
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
Evan Cheng
991f885915
- Add some NEON ld / st instruction static encoding.
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- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
llvm-svn: 75065
2009-07-08 22:51:32 +00:00
Evan Cheng
ef49d9c75b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
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llvm-svn: 75048
2009-07-08 21:03:57 +00:00
Torok Edwin
4df7c24e06
Missed an exit during the conversion.
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Will convert assert(0) that don't have abort() to LLVM_UNREACHABLE in a later
commit.
llvm-svn: 75045
2009-07-08 20:55:50 +00:00
Torok Edwin
358888da3a
Implement changes from Chris's feedback.
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Finish converting lib/Target.
llvm-svn: 75043
2009-07-08 20:53:28 +00:00
Bob Wilson
8d4a8b9370
Implement NEON vst1 instruction.
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llvm-svn: 75037
2009-07-08 20:32:02 +00:00
David Goodwin
94209a4c31
Generalize opcode selection in ARMBaseRegisterInfo.
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llvm-svn: 75036
2009-07-08 20:28:28 +00:00
Xerxes Ranby
626b0317a9
Fix cmake build.
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Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt
llvm-svn: 75035
2009-07-08 20:13:41 +00:00
David Goodwin
c571c4b457
Push methods into base class in preparation for sharing.
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llvm-svn: 75020
2009-07-08 18:31:39 +00:00
Bob Wilson
3809b333de
Implement NEON vld1 instructions.
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llvm-svn: 75019
2009-07-08 18:11:30 +00:00
Torok Edwin
ad3be984b7
Start converting to new error handling API.
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cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
llvm-svn: 75018
2009-07-08 18:01:40 +00:00
David Goodwin
7b4570ee1d
Start breaking out common base functionality for register info.
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llvm-svn: 75016
2009-07-08 17:28:55 +00:00
David Goodwin
5bdef4b3f7
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
Nick Lewycky
d46a7b2d22
Remove the vicmp and vfcmp instructions. Because we never had a release with
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these instructions, no autoupgrade or backwards compatibility support is
provided.
llvm-svn: 74991
2009-07-08 03:04:38 +00:00
Evan Cheng
18d70ca551
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
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llvm-svn: 74988
2009-07-08 01:46:35 +00:00
Evan Cheng
51549009b4
Add a todo.
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llvm-svn: 74976
2009-07-08 00:05:05 +00:00
Evan Cheng
835946d309
Also statically set bit 25 for BR_JT instructions.
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llvm-svn: 74974
2009-07-07 23:45:10 +00:00
Evan Cheng
834ee3625c
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.
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llvm-svn: 74972
2009-07-07 23:40:25 +00:00
Evan Cheng
393e38e44b
Add Thumb2 movcc instructions.
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llvm-svn: 74946
2009-07-07 20:39:03 +00:00
Evan Cheng
409ea11513
Add BX and BXr9 encodings. Patch by Sean Callanan.
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llvm-svn: 74938
2009-07-07 19:16:24 +00:00
Evan Cheng
fa864ab886
Add Thumb2 pkhbt / pkhtb.
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llvm-svn: 74895
2009-07-07 05:35:52 +00:00
Evan Cheng
46b98516f6
Add some more Thumb2 multiplication instructions.
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llvm-svn: 74889
2009-07-07 01:17:28 +00:00
Evan Cheng
3d69bea38e
80 col violation.
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llvm-svn: 74888
2009-07-07 01:16:41 +00:00
Evan Cheng
b70366baa4
isThumb2 really should mean thumb2 only, not thumb2+.
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llvm-svn: 74871
2009-07-06 22:29:14 +00:00
Evan Cheng
5a279bb4b2
Add bfc to armv6t2.
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llvm-svn: 74868
2009-07-06 22:23:46 +00:00
Evan Cheng
2570d8b541
Added ARM::mls for armv6t2.
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llvm-svn: 74866
2009-07-06 22:05:45 +00:00
Bruno Cardoso Lopes
38373542a1
Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
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cleanup, removed some #includes and moved Object Code Emitter out-of-line.
llvm-svn: 74813
2009-07-06 05:09:34 +00:00
Tilmann Scheller
cea3c16aa5
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
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With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
llvm-svn: 74764
2009-07-03 06:44:53 +00:00
Evan Cheng
f20e4fba49
Add thumb2 sign / zero extend with rotate instructions.
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llvm-svn: 74755
2009-07-03 01:43:10 +00:00
Evan Cheng
f3672575d6
Add Thumb2 load / store multiple instructions. Not used yet.
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llvm-svn: 74749
2009-07-03 00:18:36 +00:00
Evan Cheng
07bcde3709
t2LDR_PRE etc are loads.
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llvm-svn: 74741
2009-07-03 00:08:19 +00:00
Evan Cheng
162bd9cead
Added indexed stores.
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llvm-svn: 74740
2009-07-03 00:06:39 +00:00
Evan Cheng
fcab8e743a
Sign extending pre/post indexed loads.
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llvm-svn: 74736
2009-07-02 23:16:11 +00:00
David Goodwin
81075a5d30
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
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llvm-svn: 74731
2009-07-02 22:18:33 +00:00
Douglas Gregor
b523a25108
CMake build fixes, from Xerxes Ranby
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llvm-svn: 74720
2009-07-02 18:53:52 +00:00
Evan Cheng
dad6a41d14
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
Evan Cheng
7249bab8a5
80 col violation.
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llvm-svn: 74693
2009-07-02 06:44:30 +00:00
Evan Cheng
57bb186a0c
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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llvm-svn: 74692
2009-07-02 06:38:40 +00:00
Evan Cheng
bdf117bfac
80 col violation.
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llvm-svn: 74683
2009-07-02 01:30:04 +00:00
Evan Cheng
d9f23ceeb9
Factor out ARM indexed load matching code.
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llvm-svn: 74681
2009-07-02 01:23:32 +00:00
Bob Wilson
810a970c6f
Add a new addressing mode for NEON load/store instructions.
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llvm-svn: 74658
2009-07-01 23:16:05 +00:00
Bob Wilson
e3f8a640ac
Fix a comment typo.
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llvm-svn: 74650
2009-07-01 21:59:43 +00:00
Bob Wilson
11cddb5deb
Fix up a comment: besides the >80col lines, the operation for this
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addressing mode is encoded in the second operand, not the third.
llvm-svn: 74641
2009-07-01 21:22:45 +00:00
Bill Wendling
fdd5badace
Update comments to make it clear that the function alignment is the Log2 of the
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bytes and not bytes.
llvm-svn: 74624
2009-07-01 18:50:55 +00:00
Evan Cheng
37503e9671
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
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llvm-svn: 74580
2009-07-01 01:59:31 +00:00
Daniel Dunbar
bc3d149e98
Remove unused AsmPrinter OptLevel argument, and propogate.
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- This more or less amounts to a revert of r65379. I'm curious to know what
happened that caused this variable to become unused.
llvm-svn: 74579
2009-07-01 01:48:54 +00:00
David Goodwin
19aa5c7d51
Add PIC load and store patterns for Thumb-2.
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llvm-svn: 74577
2009-07-01 00:01:13 +00:00
David Goodwin
aa1f876954
Thumb-2 load and store double description. But nothing yet creates them.
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llvm-svn: 74566
2009-06-30 22:50:01 +00:00
Bill Wendling
c0fb316bd3
Add an "alignment" field to the MachineFunction object. It makes more sense to
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have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
llvm-svn: 74564
2009-06-30 22:38:32 +00:00
David Goodwin
5805e9aef5
Add thumb-2 store word, halfword, and byte.
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llvm-svn: 74555
2009-06-30 22:11:34 +00:00
David Goodwin
aad223dd8a
Improve Thumb-2 jump table support.
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llvm-svn: 74549
2009-06-30 19:50:22 +00:00
David Goodwin
5545d82866
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
Evan Cheng
2a527c3419
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
David Goodwin
4f53387d26
Add Thumb-2 support for TEQ amd TST.
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llvm-svn: 74468
2009-06-29 22:49:42 +00:00
David Goodwin
9e1280adf3
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
Duncan Sands
660e9c2106
Include the new file ThumbRegisterInfo.cpp to CMakeLists.txt
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to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.
llvm-svn: 74421
2009-06-29 13:11:32 +00:00
Evan Cheng
093adf3ff9
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
Anton Korobeynikov
7231e149ef
Simplify a bit
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llvm-svn: 74385
2009-06-27 12:59:03 +00:00
Anton Korobeynikov
1db77899c1
ARM refactoring. Step 2: split RegisterInfo
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llvm-svn: 74384
2009-06-27 12:16:40 +00:00
Douglas Gregor
6ee152cc94
Add ThumbInstrInfo.cpp to the CMake makefiles
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llvm-svn: 74382
2009-06-27 07:44:59 +00:00
Evan Cheng
817712377a
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
David Goodwin
e1979dfbf5
Remove outdated comment.
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llvm-svn: 74357
2009-06-26 23:39:02 +00:00
David Goodwin
90fc344e41
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
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llvm-svn: 74355
2009-06-26 23:13:13 +00:00
Anton Korobeynikov
aab56476b2
Split thumb-related stuff into separate classes.
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Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo
llvm-svn: 74329
2009-06-26 21:28:53 +00:00
David Goodwin
921faa64cd
Thumb-2 has CLZ.
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llvm-svn: 74322
2009-06-26 20:47:43 +00:00
David Goodwin
9da977f216
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
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llvm-svn: 74321
2009-06-26 20:45:56 +00:00
David Goodwin
46eb5a7a2d
ADC used to implement adde should use "adcs" opcode instead of "adc".
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llvm-svn: 74293
2009-06-26 18:07:25 +00:00
David Goodwin
877790aa5f
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
...
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
Evan Cheng
b93625f89e
Simplify predicate CarryDefIsUsed.
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llvm-svn: 74277
2009-06-26 06:10:18 +00:00
Devang Patel
a7a5664fbb
Let's ignore MDStrings also!
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llvm-svn: 74255
2009-06-26 02:26:12 +00:00
Evan Cheng
2eb1525e2a
Add a note about commuting conditional move.
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llvm-svn: 74241
2009-06-26 00:28:48 +00:00
Evan Cheng
f23c8a5c8a
These are done / no longer applicable.
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llvm-svn: 74239
2009-06-26 00:25:27 +00:00
Evan Cheng
4f0e461e97
Mark a bunch of instructions commutable.
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llvm-svn: 74237
2009-06-26 00:19:44 +00:00
Evan Cheng
e45355b804
tst is also commutable.
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llvm-svn: 74236
2009-06-26 00:19:07 +00:00
Evan Cheng
4ac765118d
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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llvm-svn: 74228
2009-06-25 23:34:10 +00:00
David Goodwin
74414108e9
Use MVN for ~t2_so_imm immediates.
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llvm-svn: 74223
2009-06-25 23:11:21 +00:00
David Goodwin
a0ed5f6847
Add Def/Use of CPSR for Thumb-1 instructions.
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llvm-svn: 74219
2009-06-25 22:49:55 +00:00
Evan Cheng
331e7cc684
Unbreak mingw build. Patch by Viktor Kutuzov.
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llvm-svn: 74212
2009-06-25 22:04:44 +00:00
Evan Cheng
0cced3daa8
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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llvm-svn: 74200
2009-06-25 20:59:23 +00:00
David Goodwin
c72bad36d7
Test commit
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llvm-svn: 74185
2009-06-25 17:52:32 +00:00
Bob Wilson
38779c951a
Revert 74164. We'll want to use this method later.
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llvm-svn: 74176
2009-06-25 16:03:07 +00:00
Bob Wilson
ef8fd818bf
Remove unused hasV6T2Ops method. We already have a separate feature to
...
identify Thumb2.
llvm-svn: 74164
2009-06-25 05:20:31 +00:00
Douglas Gregor
7841f61ced
Add missing dependencies to the CMake build system.
...
llvm-svn: 74161
2009-06-25 05:03:06 +00:00
Evan Cheng
a3be8cba60
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
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llvm-svn: 74158
2009-06-25 02:08:06 +00:00
Evan Cheng
e31583bf2a
Add thumb2 add sp.
...
llvm-svn: 74156
2009-06-25 01:21:30 +00:00
Evan Cheng
8e61610960
Some reorg and additional comments.
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llvm-svn: 74152
2009-06-25 01:05:06 +00:00
Devang Patel
d98b076409
No need to code gen MDNodes
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llvm-svn: 74150
2009-06-25 00:47:42 +00:00
Evan Cheng
e8c58ee743
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
Evan Cheng
32695e2413
80 col violation.
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llvm-svn: 74138
2009-06-24 23:14:45 +00:00
Chris Lattner
d59a5b9f8b
sink dwarf finalization out of each target into AsmPrinter::doFinalization
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llvm-svn: 74097
2009-06-24 18:54:37 +00:00
Chris Lattner
0690755320
eliminate the ExtWeakSymbols set from AsmPrinter. This eliminates
...
a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.
llvm-svn: 74096
2009-06-24 18:52:01 +00:00
Nick Lewycky
68273b013b
Unbreak build on Linux by removing Darwinism.
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llvm-svn: 74046
2009-06-24 01:08:42 +00:00
Dan Gohman
661e8b54fa
Revert this accidental commit.
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llvm-svn: 74042
2009-06-24 00:55:55 +00:00
Dan Gohman
3bf5d76081
Move the special cases for constants out of getUnknown and into
...
createSCEV. Also, recognize UndefValue in createSCEV.
Change getIntegerSCEV's comment to avoid mentioning FP types,
and re-implement it in terms of getConstant instead of getUnknown.
llvm-svn: 74041
2009-06-24 00:54:57 +00:00
Bob Wilson
7bd642b80c
Provide InitializeAllTargets and InitializeNativeTarget functions in the
...
C bindings. Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.
llvm-svn: 74026
2009-06-23 23:59:40 +00:00
Evan Cheng
4dcc3bd23b
Test instructions operands were printed in the wrong order.
...
llvm-svn: 73990
2009-06-23 19:56:37 +00:00
Evan Cheng
eaad82627b
Proper patterns for thumb2 shift and rotate instructions.
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llvm-svn: 73987
2009-06-23 19:39:13 +00:00
Evan Cheng
4fc8a75ae1
Code clean up.
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llvm-svn: 73986
2009-06-23 19:38:34 +00:00
Evan Cheng
1333ee8eb6
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
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llvm-svn: 73985
2009-06-23 19:38:13 +00:00
Evan Cheng
b7077f2943
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
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llvm-svn: 73975
2009-06-23 18:14:38 +00:00
Douglas Gregor
3ca1e68417
Eliminate object-relinking support from CMake. Fixes PR 4429 and
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cleans up the CMake-based build system a bit. Started by a patch from
Xerxes Rånby.
llvm-svn: 73969
2009-06-23 17:57:35 +00:00
Evan Cheng
73e4b03dc8
Obvious typo.
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llvm-svn: 73967
2009-06-23 17:54:26 +00:00
Evan Cheng
3e8033f7f7
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
...
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
llvm-svn: 73965
2009-06-23 17:48:47 +00:00
Evan Cheng
e950c375ea
Minor reorg.
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llvm-svn: 73948
2009-06-23 05:25:29 +00:00
Evan Cheng
92a49d75e4
Replace isTwoAddress with operand constraint.
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llvm-svn: 73947
2009-06-23 05:23:49 +00:00
Bob Wilson
6db76aaf10
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
Bob Wilson
48de87abcb
Add explicit types for shift count constants. This is in preparation for
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another change that makes the types ambiguous (at least as far as tablegen
is concerned).
llvm-svn: 73909
2009-06-22 22:08:29 +00:00
Bob Wilson
6e81f12950
Use thumb2 for ARM architectures V6T2 and later. Fix a bug in checking
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for "thumb" and add a check for V6T2.
llvm-svn: 73905
2009-06-22 21:28:22 +00:00
Bob Wilson
0c2c5f65e2
For Darwin on ARMv6 and newer, make register r9 available for use as a
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caller-saved register.
llvm-svn: 73901
2009-06-22 21:01:46 +00:00
Evan Cheng
b37e7e24d0
hasFP should return true if frame address is taken.
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llvm-svn: 73893
2009-06-22 18:38:48 +00:00
Bob Wilson
c859e1c6bb
Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops
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predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.
llvm-svn: 73887
2009-06-22 17:29:13 +00:00
Devang Patel
a011b501a0
Remove unused field.
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llvm-svn: 73815
2009-06-20 01:07:54 +00:00
Evan Cheng
f18de63563
Enable arm pre-allocation load / store multiple optimization pass.
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llvm-svn: 73791
2009-06-19 23:17:27 +00:00
Devang Patel
35810cd07b
Move up dwarf writer initialization in common AsmPrinter class.
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llvm-svn: 73784
2009-06-19 21:54:26 +00:00
Evan Cheng
706927c96a
Add comments.
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llvm-svn: 73761
2009-06-19 07:06:07 +00:00
Evan Cheng
8f613095de
Should be using Bcc (average) latency to determine if-conversion threshold, not BL.
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llvm-svn: 73759
2009-06-19 06:56:26 +00:00
Evan Cheng
667924dc46
Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.
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llvm-svn: 73749
2009-06-19 01:59:04 +00:00
Evan Cheng
f671ce4eba
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
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llvm-svn: 73747
2009-06-19 01:51:50 +00:00
Eli Friedman
003abaa60d
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
llvm-svn: 73746
2009-06-19 01:43:08 +00:00
Chris Lattner
c2b0fd0304
merge the common darwin settings from the X86/PPC/ARM targets
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into DarwinTargetAsmInfo.cpp. The remaining differences should
be evaluated. It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.
llvm-svn: 73742
2009-06-19 00:08:39 +00:00
Chris Lattner
6cd267dcc5
move mangler quote handling from asm printers to TargetAsmInfo.
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llvm-svn: 73738
2009-06-18 23:41:35 +00:00
Chris Lattner
ea0ea2f4bc
simplify macro debug info directive handling.
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llvm-svn: 73736
2009-06-18 23:31:37 +00:00
Evan Cheng
7426d278ae
Remove UseThumbBacktraces. Just check if subtarget is darwin.
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llvm-svn: 73734
2009-06-18 23:14:30 +00:00
Evan Cheng
6c1c55f942
On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
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llvm-svn: 73720
2009-06-18 20:37:15 +00:00
Evan Cheng
82a8ab8a8e
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
...
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
llvm-svn: 73671
2009-06-18 02:04:01 +00:00
Bob Wilson
1866500851
ARM unified syntax is not specific to ELF; use it for Darwin, too.
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llvm-svn: 73665
2009-06-18 00:36:17 +00:00
Anton Korobeynikov
dbb79a8409
Fix asm string from MOVi16
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llvm-svn: 73661
2009-06-17 23:43:36 +00:00
Anton Korobeynikov
4e0c3634cc
Thumb2 instructions are enabled only in unified assembler mode.
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Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.
llvm-svn: 73660
2009-06-17 23:43:18 +00:00
Anton Korobeynikov
7fd29c57a8
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
Douglas Gregor
f5291553f2
Introduce new headers whose inclusion forces linking and
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initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.
llvm-svn: 73543
2009-06-16 20:12:29 +00:00
Anton Korobeynikov
cc8d0058e2
Address review comments: add 3 ARM calling conventions.
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Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.
llvm-svn: 73530
2009-06-16 18:50:49 +00:00
Anton Korobeynikov
a74b8323d0
GNU as refuses to assemble "pop {}" instruction. Do not emit such
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(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
llvm-svn: 73529
2009-06-16 18:49:08 +00:00
Evan Cheng
b89602d382
On Darwin, frame pointer r7 is never available.
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llvm-svn: 73434
2009-06-15 22:32:01 +00:00
Anton Korobeynikov
2670a363da
Rename methods for the sake of consistency.
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llvm-svn: 73428
2009-06-15 21:46:20 +00:00
Evan Cheng
c007d30aad
Typo.
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llvm-svn: 73422
2009-06-15 21:18:20 +00:00
Evan Cheng
659d2536b8
Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
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llvm-svn: 73413
2009-06-15 20:54:56 +00:00
Evan Cheng
9c5f793659
Silence a warning.
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llvm-svn: 73406
2009-06-15 19:36:32 +00:00
Evan Cheng
3219c7fbe5
Part 1.
...
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
2009-06-15 08:28:29 +00:00
Evan Cheng
d0a66e438f
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
...
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
llvm-svn: 73291
2009-06-13 09:12:55 +00:00
Evan Cheng
2f784781aa
Mark some pattern-less instructions as neverHasSideEffects.
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llvm-svn: 73252
2009-06-12 20:46:18 +00:00
Anton Korobeynikov
6dbf7b689c
Typo
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llvm-svn: 73098
2009-06-08 22:59:50 +00:00
Anton Korobeynikov
0677cee20d
Revert hunk commited by accident
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llvm-svn: 73097
2009-06-08 22:57:18 +00:00
Anton Korobeynikov
d08df21f36
The attached patches implement most of the ARM AAPCS-VFP hard float
...
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
llvm-svn: 73095
2009-06-08 22:53:56 +00:00
Anton Korobeynikov
52b2898854
Separate V6 from V6T2 since the latter has some extra nice instructions
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llvm-svn: 73085
2009-06-08 21:20:36 +00:00
Anton Korobeynikov
7e9e1b3e1f
Add helper for checking of Thumb1 mode
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llvm-svn: 73080
2009-06-08 20:31:02 +00:00
Dan Gohman
e0d593cbf6
Add explicit keywords.
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llvm-svn: 72969
2009-06-05 23:05:51 +00:00
Evan Cheng
ea31ec569b
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
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llvm-svn: 72955
2009-06-05 19:08:58 +00:00
Evan Cheng
35a504c6e9
When merging multiple load / store instructions. Use the DebugLoc of the first one.
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llvm-svn: 72952
2009-06-05 18:19:23 +00:00
Evan Cheng
d240854a82
Code clean up: return vector by reference rather than by value. No functionality changes.
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llvm-svn: 72950
2009-06-05 17:56:14 +00:00
Dan Gohman
ee407d25ca
Remove some unnecessary #includes.
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llvm-svn: 72948
2009-06-05 16:32:58 +00:00
Evan Cheng
e3a05e6690
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
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llvm-svn: 72826
2009-06-04 01:15:28 +00:00
Evan Cheng
82f8fa333e
Temporarily revert 72756 for now.
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llvm-svn: 72757
2009-06-03 07:40:47 +00:00
Evan Cheng
5afbef29fa
Fold preceding / trailing base inc / dec into the single load / store as well.
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llvm-svn: 72756
2009-06-03 06:14:58 +00:00
Anton Korobeynikov
e7e9118514
Implement review feedback. Make thumb2 'normal' subtarget feature
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llvm-svn: 72698
2009-06-01 20:00:48 +00:00
Bruno Cardoso Lopes
7765059062
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
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llvm-svn: 72697
2009-06-01 19:57:37 +00:00
Anton Korobeynikov
f6ec078b26
Do not emit "generic" CPU string. This fixes PR4291.
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llvm-svn: 72696
2009-06-01 19:03:17 +00:00
Bruno Cardoso Lopes
4da7e7af43
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
...
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
llvm-svn: 72631
2009-05-30 20:51:52 +00:00
Bill Wendling
8235a05c1a
Untabification.
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llvm-svn: 72604
2009-05-30 01:09:53 +00:00
Anton Korobeynikov
4f5b1ef545
Add placeholder for thumb2 stuff
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llvm-svn: 72593
2009-05-29 23:41:08 +00:00
Chris Lattner
10cac1a776
fix typo
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llvm-svn: 72395
2009-05-25 19:51:07 +00:00
Anton Korobeynikov
1fe3d6d47b
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
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llvm-svn: 72337
2009-05-23 19:51:43 +00:00
Anton Korobeynikov
c16f747585
Emit ARM Build Attributes
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llvm-svn: 72336
2009-05-23 19:51:20 +00:00
Anton Korobeynikov
34fc85e2ee
Propagate CPU string out of SubtargetFeatures
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llvm-svn: 72335
2009-05-23 19:50:50 +00:00
Bob Wilson
372984e7a2
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
...
for ARM. This fixes rdar://6908807.
llvm-svn: 72269
2009-05-22 17:38:41 +00:00
Bob Wilson
0ac9317588
Minor formatting fixes.
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llvm-svn: 72172
2009-05-20 16:30:25 +00:00
Bob Wilson
ba6b02b54b
Fix pr4227: Handle large immediate values in inline assembly.
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llvm-svn: 72138
2009-05-19 21:27:57 +00:00
Bob Wilson
5e7a2b4ff8
Follow up on new support for memory operands in ARM inline assembly.
...
This fixes pr4233.
llvm-svn: 72115
2009-05-19 18:33:02 +00:00
Bob Wilson
c6726ecca5
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
...
the stack. Patch by Sandeep Patel.
llvm-svn: 72106
2009-05-19 10:02:36 +00:00
Bob Wilson
ec676a76e7
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
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llvm-svn: 72105
2009-05-19 05:53:42 +00:00
Bob Wilson
51e9d81e72
Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has
...
to run last because it needs to know the exact size and position of every
basic block. Currently CodePlacementOpt is set up to run last. It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.
llvm-svn: 72037
2009-05-18 20:55:32 +00:00
Jim Grosbach
bed3aeff20
Update the names of the exception handling sjlj instrinsics to
...
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
llvm-svn: 71758
2009-05-14 00:46:35 +00:00
Jim Grosbach
024feec42e
Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places
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llvm-svn: 71735
2009-05-13 22:32:43 +00:00
Evan Cheng
9bd08f0cde
Run code placement optimization for targets that want it (arm and x86 for now).
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llvm-svn: 71726
2009-05-13 21:42:09 +00:00