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Author SHA1 Message Date
Gabor Greif
c33bc67100 typo in comment, regeneration not necessary 
llvm-svn: 107774
 2010-07-07 13:58:46 +00:00
Gabor Greif
600c671ab6 conditionalize by CallInst::ArgOffset 
llvm-svn: 107767
 2010-07-07 10:34:03 +00:00
Gabor Greif
a01cb6f114 conditionalize on CallInst::ArgOffset 
llvm-svn: 107766
 2010-07-07 09:43:45 +00:00
Gabor Greif
886389fe30 minor cosmetic changes that happened to sit in my tree 
llvm-svn: 107764
 2010-07-07 09:29:07 +00:00
Duncan Sands
eb15d2084a Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts" 
builds to "Release".  The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts.  The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown).  This will bring them
in line with MacOS releases, which ship with assertions disabled.  It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.

llvm-svn: 107758
 2010-07-07 07:48:00 +00:00
Bruno Cardoso Lopes
6222076cd1 Add AVX SSE4.2 instructions 
llvm-svn: 107752
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
931471d7e8 Use only one multiclass to pinsrq instructions 
llvm-svn: 107750
 2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
65fbd0530f Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes 
llvm-svn: 107749
 2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
675ebe2dc0 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
llvm-svn: 107747
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
fa10461265 Add AVX SSE4.1 extractps and pinsr instructions 
llvm-svn: 107746
 2010-07-07 01:01:13 +00:00
Jakob Stoklund Olesen
3f4e5779d7 Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 
Buildbot breakage.

llvm-svn: 107744
 2010-07-07 00:32:25 +00:00
Bob Wilson
822b21f0de Also use REG_SEQUENCE for VTBX instructions. 
llvm-svn: 107743
 2010-07-07 00:08:54 +00:00
Jim Grosbach
71b7efe8ad Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where 
they've been tested to work.

llvm-svn: 107742
 2010-07-07 00:07:57 +00:00
Bruno Cardoso Lopes
54c2f858b3 Add AVX SSE4.1 Extract Integer instructions 
llvm-svn: 107740
 2010-07-07 00:07:24 +00:00
Jim Grosbach
657ab4a8ee By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather 
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

llvm-svn: 107734
 2010-07-06 23:44:52 +00:00
Jakob Stoklund Olesen
04124836b5 Remove references to INSERT_SUBREG after de-SSA 
llvm-svn: 107732
 2010-07-06 23:40:35 +00:00
Bob Wilson
ce80768ebf Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be 
allocated to consecutive registers.

llvm-svn: 107730
 2010-07-06 23:36:25 +00:00
Dale Johannesen
81ea05c193 Accept RIP-relative symbols with 'i' constraint, and 
print the (%rip) only if the 'a' modifier is present.
PR 7528.

llvm-svn: 107727
 2010-07-06 23:27:00 +00:00
Jakob Stoklund Olesen
83ab844c9b Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass. 
INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

llvm-svn: 107726
 2010-07-06 23:26:25 +00:00
Jakob Stoklund Olesen
44c333e87c Track defs for all aliases in NEONMoveFix. 
This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725
 2010-07-06 23:26:23 +00:00
Bruno Cardoso Lopes
b9e1c33054 Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107723
 2010-07-06 23:15:17 +00:00
Dale Johannesen
f06021547c Make test not hang waiting for input. 
llvm-svn: 107721
 2010-07-06 23:06:58 +00:00
Bruno Cardoso Lopes
0c6ec0b068 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107720
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
af8968696a Fix comment from previous patch 
llvm-svn: 107717
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes
a0b37e839c Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Dan Gohman
d409104054 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext. 
SelectBasicBlock doesn't needs its BasicBlock argument.

llvm-svn: 107712
 2010-07-06 22:19:37 +00:00
Devang Patel
7ab104353b Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Bob Wilson
084a11cb59 Represent NEON load/store alignments in bytes, not bits. 
llvm-svn: 107701
 2010-07-06 21:26:18 +00:00
Jakob Stoklund Olesen
bc4a57ef56 One more case assuming that subregs have live ranges. 
llvm-svn: 107700
 2010-07-06 21:13:03 +00:00
John McCall
a59e143fec Closing tags start with slashes. 
llvm-svn: 107699
 2010-07-06 21:07:14 +00:00
Jakob Stoklund Olesen
ec2c876e57 Fix buildbot breakage where a def is missing. 
llvm-svn: 107698
 2010-07-06 21:06:39 +00:00
Devang Patel
568037d823 Add fixme. 
llvm-svn: 107697
 2010-07-06 21:05:17 +00:00
Chris Lattner
3139b75beb minor typo 
llvm-svn: 107696
 2010-07-06 20:51:35 +00:00
Jakob Stoklund Olesen
f86de96f78 Be more forgiving when calculating alias interference for physreg coalescing. 
It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.

This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.

llvm-svn: 107695
 2010-07-06 20:31:51 +00:00
Dan Gohman
808f334f79 Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691
 2010-07-06 20:24:04 +00:00
Matt Fleming
33be71076b Add X86_64 ELF relocation values and ELF64 relocation classes. 
Patch from Roman Divacky.

llvm-svn: 107688
 2010-07-06 18:44:02 +00:00
Matt Fleming
529618a11d Add some more ELF OSABI values as found in the System V Application 
Binary Interface specification.

llvm-svn: 107685
 2010-07-06 18:36:57 +00:00
Eric Christopher
383df15267 Fix to 80-col. 
llvm-svn: 107684
 2010-07-06 18:35:20 +00:00
John McCall
0e0d4bcfc8 Provide IRBuilder conveniences for creating integer constants at common widths, 
and give a more precise return type for some of the type-creation methods.

llvm-svn: 107683
 2010-07-06 18:34:49 +00:00
Nick Lewycky
529cb5fcd1 Alphabetize the list of function parameters. 
llvm-svn: 107680
 2010-07-06 18:24:09 +00:00
Devang Patel
ffc54b23fe Fix PR7545 crash. 
llvm-svn: 107678
 2010-07-06 18:18:32 +00:00
John McCall
2b36dbadb8 Provide an abstraction to save and restore the current insertion point of 
an IRBuilder.

llvm-svn: 107677
 2010-07-06 18:07:52 +00:00
Rafael Espindola
e5689571a1 Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion 
if profitable.

llvm-svn: 107673
 2010-07-06 16:24:34 +00:00
Chris Lattner
18ba4703b0 tighten up this code. 
llvm-svn: 107670
 2010-07-06 15:59:27 +00:00
Duncan Sands
31db6c2247 Bring the list of passes and their descriptions up to date. 
Patch by Kenneth Hoste.

llvm-svn: 107669
 2010-07-06 15:52:15 +00:00
Dan Gohman
4d264f7e51 Revert r107655. 
llvm-svn: 107668
 2010-07-06 15:49:48 +00:00
Gabor Greif
0e5792fac6 second round of low-level interface squeeze-out: 
making all of CallInst's low-level operand accessors
private

If you get compile errors I strongly urge you to
update your code.


I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.

You have several options to update your code:

- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
  low-level accessors if your code is definitely
  operand-order agnostic.

If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):

<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>

llvm-svn: 107667
 2010-07-06 15:44:11 +00:00
Dan Gohman
38f2820fc3 Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands 
which do not depend on SelectionDAG.

llvm-svn: 107666
 2010-07-06 15:39:54 +00:00
Dan Gohman
66125b8df0 Add a new CCValAssign LocInfo value, and a comment explaining what it 
should be used for.

llvm-svn: 107661
 2010-07-06 15:35:06 +00:00
Dan Gohman
c88c36181f Make getMinimalPhysRegClass' comment mention what makes it different 
from getPhysicalRegisterRegClass.

llvm-svn: 107660
 2010-07-06 15:31:55 +00:00