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Commit Graph

1419 Commits

Author SHA1 Message Date
Evan Cheng
783028063e Shrinkify Thumb2 load / store multiple instructions.
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
2009-08-11 20:47:22 +00:00
Chris Lattner
30d9c39337 pass the TargetTriple down from each target ctor to the
LLVMTargetMachine ctor.  It is currently unused.

llvm-svn: 78711
2009-08-11 20:42:37 +00:00
Chris Lattner
45bdc96988 split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
version.  This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.

The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.

llvm-svn: 78709
2009-08-11 20:30:58 +00:00
Jim Grosbach
67841ae0a8 Add Thumb2 eh_sjlj_setjmp implementation
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
Jim Grosbach
c80da41574 fix GetInstSizeInBytes for eh_sjlj_setjmp
llvm-svn: 78683
2009-08-11 17:08:15 +00:00
Benjamin Kramer
0481803d2a This void is implicit in C++.
llvm-svn: 78678
2009-08-11 16:03:08 +00:00
Jim Grosbach
3c898a99bd Whitespace cleanup. Remove trailing whitespace.
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
Jim Grosbach
d5fc7e81b2 Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header.
llvm-svn: 78665
2009-08-11 15:26:27 +00:00
Evan Cheng
249f07cf57 Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
llvm-svn: 78659
2009-08-11 09:37:40 +00:00
Evan Cheng
434a66fa9b Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658
2009-08-11 08:52:18 +00:00
Evan Cheng
9fdf9b4435 80 column violation.
llvm-svn: 78657
2009-08-11 08:47:46 +00:00
Evan Cheng
766c076bea Cosmetic changes.
llvm-svn: 78655
2009-08-11 07:36:14 +00:00
Evan Cheng
dbccf353d1 Adding a blank line back.
llvm-svn: 78654
2009-08-11 07:32:58 +00:00
Bob Wilson
d64e304671 Use vAny type to get rid of Neon intrinsics that differed only in whether
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
2009-08-11 05:39:44 +00:00
Bob Wilson
1c75a23299 Use new EVT::vAny type to combine Neon intrinsics for VPADD.
llvm-svn: 78632
2009-08-11 01:15:26 +00:00
David Goodwin
8ca187462c Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
llvm-svn: 78629
2009-08-11 01:07:38 +00:00
Jim Grosbach
c2fd915309 Add stdlib.h
llvm-svn: 78627
2009-08-11 00:20:00 +00:00
Jim Grosbach
c9a1dd9291 SjLj based exception handling unwinding support. This patch is nasty, brutish
and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625
2009-08-11 00:09:57 +00:00
Evan Cheng
49aac700f4 Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
llvm-svn: 78622
2009-08-10 23:56:04 +00:00
Dan Gohman
888bcd3483 Fix a bug where DAGCombine was producing an illegal ConstantFP
node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615
2009-08-10 23:15:10 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
David Goodwin
36a5b02e4f Use NEON for single-precision int<->FP conversions.
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
Owen Anderson
30bf6c8dab SimpleValueType-ify a few more methods on TargetLowering.
llvm-svn: 78595
2009-08-10 20:46:15 +00:00
Evan Cheng
f0bb0f5204 Handle the constantfp created during post-legalization dag combiner phase.
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
Owen Anderson
cf56d576eb Continue the SimpleValueType-ification.
llvm-svn: 78593
2009-08-10 20:18:46 +00:00
Chris Lattner
3e6da637f6 split MachO section handling stuff out to its out .h/.cpp file.
llvm-svn: 78576
2009-08-10 18:15:01 +00:00
Chris Lattner
7abff8fdb4 arm only needs to emit one .align directive for hidden nlp's, not one
per pointer.

llvm-svn: 78574
2009-08-10 18:02:16 +00:00
Chris Lattner
b89551026b make sure that arm nonlazypointers are aligned properly
llvm-svn: 78573
2009-08-10 18:01:34 +00:00
David Goodwin
b2f53ed68a Checkpoint scheduling itinerary changes.
llvm-svn: 78564
2009-08-10 15:56:13 +00:00
Evan Cheng
0a08d1bb9c Watch out for empty BB.
llvm-svn: 78562
2009-08-10 08:10:13 +00:00
Evan Cheng
1ecffadc8d rev, rev16, and revsh do not set CPSR.
llvm-svn: 78561
2009-08-10 07:58:45 +00:00
Evan Cheng
87030de948 Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
llvm-svn: 78560
2009-08-10 07:20:37 +00:00
Evan Cheng
e76bc4a520 CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
llvm-svn: 78559
2009-08-10 06:57:42 +00:00
Evan Cheng
b0a0b99918 Add support for folding loads / stores into 16-bit moves used by Thumb2.
llvm-svn: 78558
2009-08-10 06:32:05 +00:00
Evan Cheng
b05ad1d066 80 col violation.
llvm-svn: 78557
2009-08-10 05:51:48 +00:00
Evan Cheng
f54e50e4e8 Use tMOVgpr2gpr instead of t2MOVr.
llvm-svn: 78556
2009-08-10 05:49:43 +00:00
Evan Cheng
ad380aa97a Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
llvm-svn: 78550
2009-08-10 02:37:24 +00:00
Evan Cheng
09cacea9fb Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
llvm-svn: 78549
2009-08-10 02:06:53 +00:00
Chris Lattner
cc70d578be Make the big switch: Change MCSectionMachO to represent a section *semantically*
instead of syntactically as a string.  This means that it keeps track of the 
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and 
"attribute(section)", so we should now start getting errors about invalid 
section attributes from the compiler instead of the assembler on darwin.

Still todo: 
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
   S_GB_ZEROFILL segment type?

llvm-svn: 78547
2009-08-10 01:39:42 +00:00
Evan Cheng
390e1927bf Add support to convert 32-bit instructions to 16-bit non-two-address ones.
llvm-svn: 78540
2009-08-09 19:17:19 +00:00
Anton Korobeynikov
44fa9f179c Use subclassing to print lane-like immediates (w/o hash) eliminating
'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514
2009-08-08 23:10:41 +00:00
Chris Lattner
2849883bd5 1. Make MCSection an abstract class.
2. Move section switch printing to MCSection virtual method which takes a
   TAI.  This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and 
   TLOFELF::AtIsCommentChar.

llvm-svn: 78510
2009-08-08 22:41:53 +00:00
Chris Lattner
1e8ed03507 now that getOrCreateSection is all object-file specific,
give the impls an object-file-specific name.  In the future
they can take different arguments etc.

llvm-svn: 78495
2009-08-08 20:22:20 +00:00
Daniel Dunbar
63159fdd2c Update CMake
llvm-svn: 78475
2009-08-08 17:03:13 +00:00
Anton Korobeynikov
f8256ecbb5 Add insert_elt / extract_elt patterns for v4f32 stuff.
Did anyone tests v4f32 ever?

llvm-svn: 78470
2009-08-08 14:06:07 +00:00
Anton Korobeynikov
0471ef8dd6 Lane number should be printed w/o hash
llvm-svn: 78469
2009-08-08 14:05:53 +00:00
Anton Korobeynikov
ae22c37afb Use VLDM / VSTM to spill/reload 128-bit Neon registers
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
Bob Wilson
88fafd84ea Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460
2009-08-08 06:13:25 +00:00
Bob Wilson
935ee0c122 Implement Neon VTRN instructions. For now, anyway, these are selected
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459
2009-08-08 05:53:00 +00:00