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208449 Commits

Author SHA1 Message Date
Fangrui Song
04f2a7afd9 [AArch64InstPrinter] Change printADRPLabel to print the target address in hexadecimal form
Similar to D77853. Change ADRP to print the target address in hex, instead of the raw immediate.
The behavior is similar to GNU objdump but we also include `0x`.

Note: GNU objdump is not consistent whether or not to emit `0x` for different architectures. We try emitting 0x consistently for all targets.

```
GNU objdump:       adrp x16, 10000000
Old llvm-objdump:  adrp x16, #0
New llvm-objdump:  adrp x16, 0x10000000
```

`adrp Xd, 0x...` assembles to a relocation referencing `*ABS*+0x10000` which is not intended. We need to use a linker or use yaml2obj.
The main test is `test/tools/llvm-objdump/ELF/AArch64/pcrel-address.yaml`

Differential Revision: https://reviews.llvm.org/D93241
2020-12-16 09:20:55 -08:00
Esme-Yi
13ee52e4a2 Revert "[PowerPC] Extend folding RLWINM + RLWINM to post-RA."
This reverts commit 1c0941e1524f499e3fbde48fc3bdd0e70fc8f2e4.
2020-12-16 17:12:24 +00:00
Whitney Tsang
1fd321cbfa [LoopNest] Handle loop-nest passes in LoopPassManager
Per http://llvm.org/OpenProjects.html#llvm_loopnest, the goal of this
patch (and other following patches) is to create facilities that allow
implementing loop nest passes that run on top-level loop nests for the
New Pass Manager.

This patch extends the functionality of LoopPassManager to handle
loop-nest passes by specializing the definition of LoopPassManager that
accepts both kinds of passes in addPass.

Only loop passes are executed if L is not a top-level one, and both
kinds of passes are executed if L is top-level. Currently, loop nest
passes should have the following run method:

PreservedAnalyses run(LoopNest &, LoopAnalysisManager &,
LoopStandardAnalysisResults &, LPMUpdater &);

Reviewed By: Whitney, ychen
Differential Revision: https://reviews.llvm.org/D87045
2020-12-16 17:07:14 +00:00
Jonas Hahnfeld
4ec8628b1a [CMake] Avoid __FakeVCSRevision.h with no git repository
Set the return variable to "" in find_first_existing_vc_file to
say that there is a repository, but no file to depend on. This works
transparently for all other callers that handle undefinedness and
equality to an empty string the same way.

Use the knowledge to avoid depending on __FakeVCSRevision.h if there
is no git repository at all (for example when building a release) as
there is no point in regenerating an empty VCSRevision.h.

Differential Revision: https://reviews.llvm.org/D92718
2020-12-16 17:33:20 +01:00
Kai Nacke
3d56a7203c [Doc][SystemZ] Add Linux/SystemZ to Getting Started guide.
The Linux/SystemZ platform is missing in the Getting Started guide
as platform on which LLVM is known to work.

Reviewed by: uweigand

Differential Revision: https://reviews.llvm.org/D93388
2020-12-16 10:46:05 -05:00
Florian Hahn
70b11cbecd [InstCombine] Precommit tests for !annotation metadata handling. 2020-12-16 15:43:30 +00:00
Matt Arsenault
a6f5a606fa LangRef: Update byval/sret description for required types 2020-12-16 10:25:36 -05:00
Paul C. Anagnostopoulos
0f58806903 [TableGen] Slim down the data structures in xxxGenInstrInfo.inc, step 1 2020-12-16 09:57:43 -05:00
Simon Pilgrim
0fedcd35f9 [X86] Regenerate bit extraction tests, cleaning up check-prefixes.
As noticed on D92965, we needed to simplify the prefixes to ensure all RUNs were properly covered.

We should never have a target with BMI2 without BMI1, so use that as the 'BMI level' and then check with/without TBM (all TBM targets have at least BMI1).
2020-12-16 14:48:21 +00:00
Simon Pilgrim
11bb7ac1f0 [X86] Rename reduction combiners to make it clearer whats happening. NFCI.
Since these are all working on reduction patterns, actually use that term in the function name to make them easier to search for.

At some point we're likely to start working with the ISD::VECREDUCE_* opcodes directly in the x86 backend, but that is still some way off.
2020-12-16 14:48:21 +00:00
diggerlin
44531d9a39 [XCOFF][AIX] Emit EH information in traceback table
SUMMARY:

In order for the runtime on AIX to find the compact unwind section(EHInfo table),
we would need to set the following on the traceback table:

The 6th byte's longtbtable field to true to signal there is an Extended TB Table Flag.
The Extended TB Table Flag to be 0x08 to signal there is an exception handling info presents.
Emit the offset between ehinfo TC entry and TOC base after all other optional portions of traceback table.

The patch is authored by Jason Liu.

Reviewers: David Tenty, Digger Lin
Differential Revision: https://reviews.llvm.org/D92766
2020-12-16 09:34:59 -05:00
Caroline Concatto
cdf5a430ee [SLPVectorizer]Migrate getEntryCost to return InstructionCost
This patch also changes:
  the return type of getGatherCost and
  the signature of the debug function dumpTreeCosts
to use InstructionCost.

This patch is part of a series of patches to use InstructionCost instead of
unsigned/int for the cost model functions.

See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html

See this patch for the introduction of the type:
https://reviews.llvm.org/D91174

Depends on D93049

Differential Revision: https://reviews.llvm.org/D93127
2020-12-16 14:18:40 +00:00
Denis Antrushin
e40fd1acc9 [Statepoints] Extract invoke tests into separate file. NFC.
Extract VReg lowering tests with invokes into separate file
for easier maintenance/modification.
Check MIR after register allocation - at this point all
transformations we're interested in has been applied and verifying
of MIR is simpler than that of assembly.
2020-12-16 20:53:28 +07:00
Bradley Smith
94d6c090f7 [CostModel] Add costs for llvm.experimental.vector.{extract,insert} intrinsics
Adds cost model support for the new llvm.experimental.vector.{extract,insert}
intrinsics, using the existing getExtractSubvectorOverhead and
getInsertSubvectorOverhead functions for shuffles.

Previously this case would throw an assertion.

Differential Revision: https://reviews.llvm.org/D93043
2020-12-16 13:39:04 +00:00
Caroline Concatto
8e6567f917 [CostModel]Migrate getTreeCost() to use InstructionCost
This patch changes the type of cost variables (for instance: Cost, ExtractCost,
SpillCost) to use InstructionCost.
This patch also changes the type of cost variables to InstructionCost in other
functions that use the result of getTreeCost()
This patch is part of a series of patches to use InstructionCost instead of
unsigned/int for the cost model functions.

See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html

Depends on D91174

Differential Revision: https://reviews.llvm.org/D93049
2020-12-16 13:08:37 +00:00
Caroline Concatto
b575d6a35a [CostModel]Replace FixedVectorType by VectorType in costgetIntrinsicInstrCost
This patch replaces FixedVectorType by VectorType in getIntrinsicInstrCost
in BasicTTIImpl.h. It re-arranges the scalable type test earlier return
and add tests for scalable types.

Depends on D91532

Differential Revision: https://reviews.llvm.org/D92094
2020-12-16 13:06:23 +00:00
Joe Ellis
b9b87adf55 [clang][AArch64][SVE] Avoid going through memory for VLAT <-> VLST casts
This change makes use of the llvm.vector.extract intrinsic to avoid
going through memory when performing bitcasts between vector-length
agnostic types and vector-length specific types.

Depends on D91362

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D92761
2020-12-16 12:24:32 +00:00
Bangtian Liu
e7d3773d91 Revert "Ensure SplitEdge to return the new block between the two given blocks"
This reverts commit cf638d793c489632bbcf0ee0fbf9d0f8c76e1f48.
2020-12-16 11:52:30 +00:00
Simon Pilgrim
a19adfd9b4 [X86][SSE] combineReductionToHorizontal - don't rely on widenSubVector to handle illegal vector types.
Thanks to @asbirlea for reporting the bug.
2020-12-16 11:24:40 +00:00
Georgii Rymar
f7c776770a [yaml2obj/obj2yaml] - Make Value/Size fields of Symbol optional.
When a field is optional we can use the `=<none>` syntax in macros.
This patch makes `Value`/`Size` fields of `Symbol` optional
and adds test cases for them.

Differential revision: https://reviews.llvm.org/D93010
2020-12-16 13:49:57 +03:00
Georgii Rymar
eb12cf3add [lib/Object] - Make ELFObjectFile::getSymbol() return Expected<>.
This was requested in comments for D93209:
https://reviews.llvm.org/D93209#inline-871192

D93209 fixes an issue with `ELFFile<ELFT>::getEntry`,
after what `getSymbol` starts calling `report_fatal_error` for previously
missed invalid cases.

This patch makes it return `Expected<>` and updates callers.
For few of them I had to add new `report_fatal_error` calls. But I see no
way to avoid it currently. The change would affects too many places, e.g:
`getSymbolBinding` and other methods are used from `ELFSymbolRef`
which is used in too many places across LLVM.

Differential revision: https://reviews.llvm.org/D93297
2020-12-16 13:14:23 +03:00
Georgii Rymar
e16531589c [llvm-readelf/obj] - Handle out-of-order PT_LOADs better.
This is https://bugs.llvm.org/show_bug.cgi?id=45698.

Specification says that
"Loadable segment entries in the program header table appear
in ascending order, sorted on the p_vaddr member."

Our `toMappedAddr()` relies on this condition. This patch
adds a warning when the sorting order of loadable segments is wrong.
In this case we force segments sorting and that allows
`toMappedAddr()` to work as expected.

Differential revision: https://reviews.llvm.org/D92641
2020-12-16 12:59:32 +03:00
Piotr Sobczak
1fb1c3cd05 [AMDGPU] Avoid calling copyFastMathFlags in wrong context
Calling Instruction::copyFastMathFlags() assumes the caller is
FPMathOperator. Avoid calling the function for instructions
that are not instances of FPMathOperator.
2020-12-16 10:22:51 +01:00
Sebastian Neubauer
20ade166d1 [AMDGPU] Allow no saddr for global addtid insts
I think the global_load/store_dword_addtid instructions support
switching off the scalar address.
Add assembler and disassembler support for this.

Differential Revision: https://reviews.llvm.org/D93288
2020-12-16 10:01:40 +01:00
Jan Svoboda
53d0b253a4 [clang][cli] Prevent double denormalization
If both flags created through BoolOption are CC1Option and the keypath has a non-default or non-implied value, the denormalizer gets called twice. If the denormalizer has the ability to generate both flags, we can end up generating the same flag twice.

Reviewed By: dexonsmith, Bigcheese

Differential Revision: https://reviews.llvm.org/D93094
2020-12-16 09:44:54 +01:00
Stanislav Mekhanoshin
8688622340 [AMDGPU] Print SCRATCH_EN field after the kernel
Differential Revision: https://reviews.llvm.org/D93353
2020-12-15 22:44:30 -08:00
Philip Reames
a55c1816ea [LV] Weaken a unnecessarily strong assert [NFC]
Account for the fact that (in the future) the latch might be a switch not a branch.  The existing code is correct, minus the assert.
2020-12-15 19:07:53 -08:00
Lang Hames
36c0911571 [JITLink][ORC] Enable creation / linking of raw jitlink::LinkGraphs.
Separates link graph creation from linking. This allows raw LinkGraphs to be
created and passed to a link. ObjectLinkingLayer is updated to support emission
of raw LinkGraphs in addition to object buffers.

Raw LinkGraphs can be created by in-memory compilers to bypass object encoding /
decoding (though this prevents caching, as LinkGraphs have do not have an
on-disk representation), and by utility code to add programatically generated
data structures to the JIT target process.
2020-12-16 14:01:50 +11:00
Zakk Chen
f62c427dbf [RISCV] Refine vector load/store tablegen pattern, NFC.
Refine tablegen pattern for vector load/store, and follow
D93012 to separate masked and unmasked definitions for
pseudo load/store instructions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93284
2020-12-15 18:55:55 -08:00
Philip Reames
babb17746f [LV] Extend dead instruction detection to multiple exiting blocks
Given we haven't yet enabled multiple exiting blocks, this is currently non functional, but it's an obvious extension which cleans up a later patch.

I don't think this is worth review (as it's pretty obvious), if anyone disagrees, feel feel to revert or comment and I will.
2020-12-15 18:46:32 -08:00
Krzysztof Parzyszek
377eef9f3b [Hexagon] Rename test case, NFC 2020-12-15 19:05:31 -06:00
Krzysztof Parzyszek
7bf57c181c [Hexagon] Temporarily disable vector realignment for non-HVX vectors 2020-12-15 19:03:07 -06:00
Krzysztof Parzyszek
a31ff2abea [Hexagon] Emit enough stores when aligning vector addresses 2020-12-15 18:59:53 -06:00
LLVM GN Syncbot
f211f158cb [gn build] Port b9c77542e23 2020-12-16 00:03:26 +00:00
Johannes Doerfert
05f471417e Revert "[OpenMP] Add initial support for omp [begin/end] assumes"
There is a build error with gcc-5 [0], investigating now.

[0] https://reviews.llvm.org/D91980#2456526

This reverts commit a5a14cbe7f87e01882ecaa14df5d596cbf38823a.
2020-12-15 18:03:10 -06:00
Reid Kleckner
45f3869c8b Document that AlignedCharArrayUnion exists to work around an MSVC bug
Differential Revision: https://reviews.llvm.org/D93355
2020-12-15 16:01:55 -08:00
Bangtian Liu
e77001771a Ensure SplitEdge to return the new block between the two given blocks
This PR implements the function splitBasicBlockBefore to address an
issue
that occurred during SplitEdge(BB, Succ, ...), inside splitBlockBefore.
The issue occurs in SplitEdge when the Succ has a single predecessor
and the edge between the BB and Succ is not critical. This produces
the result ‘BB->Succ->New’. The new function splitBasicBlockBefore
was added to splitBlockBefore to handle the issue and now produces
the correct result ‘BB->New->Succ’.

Below is an example of splitting the block bb1 at its first instruction.

/// Original IR
bb0:
	br bb1
bb1:
        %0 = mul i32 1, 2
	br bb2
bb2:
/// IR after splitEdge(bb0, bb1) using splitBasicBlock
bb0:
	br bb1
bb1:
	br bb1.split
bb1.split:
        %0 = mul i32 1, 2
	br bb2
bb2:
/// IR after splitEdge(bb0, bb1) using splitBasicBlockBefore
bb0:
	br bb1.split
bb1.split
	br bb1
bb1:
        %0 = mul i32 1, 2
	br bb2
bb2:

Differential Revision: https://reviews.llvm.org/D92200
2020-12-15 23:32:29 +00:00
Harald van Dijk
7019559b57 [X86] Add REX prefix for GOTTPOFF/TLSDESC relocs in x32 mode
The REX prefix is needed to allow linker relaxations: even if the
instruction we emit may not need it, the linker may change it to a
different instruction which does need it.
2020-12-15 23:07:34 +00:00
Fangrui Song
5dd827ba56 [IR] Delete deprecated DebugLoc::get 2020-12-15 14:53:12 -08:00
Johannes Doerfert
d6a9ea03f5 [OpenMP] Add initial support for omp [begin/end] assumes
The `assumes` directive is an OpenMP 5.1 feature that allows the user to
provide assumptions to the optimizer. Assumptions can refer to
directives (`absent` and `contains` clauses), expressions (`holds`
clause), or generic properties (`no_openmp_routines`, `ext_ABCD`, ...).

The `assumes` spelling is used for assumptions in the global scope while
`assume` is used for executable contexts with an associated structured
block.

This patch only implements the global spellings. While clauses with
arguments are "accepted" by the parser, they will simply be ignored for
now. The implementation lowers the assumptions directly to the
`AssumptionAttr`.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D91980
2020-12-15 16:51:34 -06:00
Johannes Doerfert
38aa2584d5 [OpenMP] Use assumptions during ICV tracking
The OpenMP 5.1 assumptions `no_openmp` and `no_openmp_routines` allow us
to ignore calls that would otherwise prevent ICV tracking.

Once we track more ICVs we might need to distinguish the ones that could
be impacted even with `no_openmp_routines`.

Reviewed By: sstefan1

Differential Revision: https://reviews.llvm.org/D92050
2020-12-15 16:51:34 -06:00
Johannes Doerfert
6230d2a2a4 [Clang][Attr] Introduce the assume function attribute
The `assume` attribute is a way to provide additional, arbitrary
information to the optimizer. For now, assumptions are restricted to
strings which will be accumulated for a function and emitted as comma
separated string function attribute. The key of the LLVM-IR function
attribute is `llvm.assume`. Similar to `llvm.assume` and
`__builtin_assume`, the `assume` attribute provides a user defined
assumption to the compiler.

A follow up patch will introduce an LLVM-core API to query the
assumptions attached to a function. We also expect to add more options,
e.g., expression arguments, to the `assume` attribute later on.

The `omp [begin] asssumes` pragma will leverage this attribute and
expose the functionality in the absence of OpenMP.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D91979
2020-12-15 16:51:34 -06:00
Johannes Doerfert
e4d8c28959 [OpenMPOpt][NFC] Clang format 2020-12-15 16:51:34 -06:00
Matt Arsenault
b5e8fa500a RegisterCoalescer: Remove phi-only subranges when erasing identity copies
Undef subranges are not present in the live range values, except when
they cross block boundaries. In this situation, a identity copy is
inside a loop, and one of the lanes is undefined. It only appears
alive inside the loop due to the copy. Once the copy was erased, it
would leave behind a segment inside the loop body with no
corresponding def anywhere in the program.

When RenameIndependentSubregs processed this dummy interval, it would
introduce a "Multiple connected components in live interval" verifier
error when IMPLICIT_DEFs were added to the other two blocks. I believe
there is a missing verifier check for this type of dummy interval.

I have found additional cases from the same fundamental problem in
other areas I haven't managed to fix yet (e.g. the commented out
prune_subrange_phi_value_* cases).
2020-12-15 17:36:32 -05:00
Hsiangkai Wang
e9597071e5 [RISCV] Define vfadd/vfsub/vfrsub intrinsics.
Define vfadd/vfsub/vfrsub intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93291
2020-12-16 06:31:47 +08:00
Hsiangkai Wang
0f1989f2f6 [RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93218
2020-12-16 06:31:47 +08:00
Hsiangkai Wang
d53bf6755a [RISCV] Define vnsrl/vnsra intrinsics.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93207
2020-12-16 06:31:47 +08:00
Hsiangkai Wang
2ae9c17a2d [RISCV] Define vsll/vsrl/vsra intrinsics.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93193
2020-12-16 06:31:47 +08:00
Hsiangkai Wang
f62454ac21 [RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93175
2020-12-16 06:31:47 +08:00
Fangrui Song
0d6e89041d [docs][unittest][Go][StackProtector] Migrate deprecated DebugInfo::get to DILocation::get 2020-12-15 14:17:04 -08:00