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7939025262
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6313 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
7939025262 Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments 
llvm-svn: 111890
 2010-08-24 01:16:15 +00:00
Bruno Cardoso Lopes
ed9ff8d8d0 Start using target speficic nodes for shuffles: pshufhw and pshuflw 
llvm-svn: 111837
 2010-08-23 20:41:02 +00:00
Gabor Greif
6bd4b1cc6c tyops 
llvm-svn: 111835
 2010-08-23 20:30:51 +00:00
Chris Lattner
f0f35c4aea Add a new llvm.x86.int intrinsic, allowing access to the 
x86 int and int3 instructions.  Patch by Peter Housel!

llvm-svn: 111831
 2010-08-23 19:39:25 +00:00
Chris Lattner
f4dfc7aaab random improvement for variable shift codegen. 
llvm-svn: 111813
 2010-08-23 17:30:29 +00:00
Anton Korobeynikov
a68e2a53a1 Revert invalid r111792. Jump tables are not broken on x86-64 / coff, 
it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.

llvm-svn: 111801
 2010-08-23 07:38:51 +00:00
Michael J. Spencer
c52ac23659 Workaround broken jump tables on x86-64 COFF. 
llvm-svn: 111792
 2010-08-23 04:45:37 +00:00
Anton Korobeynikov
c3294e6abe Use rip-rel addressing on win64 by default. For this we just 
defaults to small pic code model.

llvm-svn: 111741
 2010-08-21 17:21:11 +00:00
Michael J. Spencer
18689045ce MC: Add partial x86-64 support to COFF. 
llvm-svn: 111728
 2010-08-21 05:58:13 +00:00
Dan Gohman
30b8e6cfd2 Fix x86 fast-isel's cmp+branch folding to avoid folding when the 
comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.

llvm-svn: 111709
 2010-08-21 02:32:36 +00:00
Bruno Cardoso Lopes
1998fbbf1a Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly 
llvm-svn: 111704
 2010-08-21 01:32:18 +00:00
Bruno Cardoso Lopes
28d9071635 This is the first step towards refactoring the x86 vector shuffle code. The 
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.

The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.

llvm-svn: 111691
 2010-08-20 22:55:05 +00:00
Chris Lattner
355d472093 fix PR7465, mishandling of lcall and ljmp: intersegment long 
call and jumps.

llvm-svn: 111496
 2010-08-19 01:18:43 +00:00
Chris Lattner
b3abfa861f minor progress towards fixing PR7465 
llvm-svn: 111494
 2010-08-19 01:00:34 +00:00
Bill Wendling
fa83b9853e Marked with ATTRIBUTE_USED so that clang doesn't complain. 
llvm-svn: 111383
 2010-08-18 18:40:57 +00:00
Chris Lattner
f94830f175 remove some code that is dead now that lea's are modeled with segment registers. 
llvm-svn: 111343
 2010-08-18 02:40:44 +00:00
Anton Korobeynikov
52c8ecf231 Revert part of one of the prev. patches - tailjmp will follow later. 
llvm-svn: 111291
 2010-08-17 21:08:28 +00:00
Anton Korobeynikov
f0600e9e8a More fixes for win64: 
- Do not clobber al during variadic calls, this is AMD64 ABI-only feature
  - Emit wincall64, where necessary
Patch by Cameron Esfahani!

llvm-svn: 111289
 2010-08-17 21:06:07 +00:00
Anton Korobeynikov
f1f88db4fd Enable more win64 calls folding opportunities. 
Patch by Cameron Esfahani!

llvm-svn: 111288
 2010-08-17 21:06:01 +00:00
Eli Friedman
515b81a494 Comment out some broken/unused/useless instructions which mess up disassembly. 
llvm-svn: 111185
 2010-08-16 21:18:51 +00:00
Eli Friedman
b9707bb261 Don't attempt to SimplifyShortMoveForm in 64-bit mode. 
llvm-svn: 111182
 2010-08-16 21:03:32 +00:00
Matt Fleming
0078681411 Hookup ELF support for X86. 
llvm-svn: 111173
 2010-08-16 18:36:14 +00:00
Jakob Stoklund Olesen
437fea641b Partially revert r111155. It looks like MSVC is calling an operator<() that 
clang says is unused.

llvm-svn: 111167
 2010-08-16 18:24:54 +00:00
Jakob Stoklund Olesen
a3eb6a36c2 Remove unused functions. 
llvm-svn: 111155
 2010-08-16 17:18:18 +00:00
Argyrios Kyrtzidis
75b69c1de3 Revert r111082. No warnings for this common pattern. 
llvm-svn: 111102
 2010-08-15 10:27:23 +00:00
Eric Christopher
1470fe415c Rework how the non-sse2 memory barrier is lowered so that the 
encoding is correct for the built-in assembler.

Based on a patch from Chris.

llvm-svn: 111083
 2010-08-14 21:51:50 +00:00
Argyrios Kyrtzidis
70b248e3ac Add ATTRIBUTE_UNUSED to methods that are not supposed to be used. 
llvm-svn: 111082
 2010-08-14 21:35:10 +00:00
Chris Lattner
8426971169 improve indentation 
llvm-svn: 111073
 2010-08-14 17:26:09 +00:00
Bruno Cardoso Lopes
1eaa601d84 Add comments to some pattern fragments in x86 
llvm-svn: 111041
 2010-08-13 20:39:01 +00:00
Dale Johannesen
3f9c148d0e Revert 110491. While not wrong, it was based on a 
misanalysis and is undesirable.

llvm-svn: 111028
 2010-08-13 18:43:45 +00:00
Bruno Cardoso Lopes
8b07859f3a Fix comment to reflect code, and remove an unused argument 
llvm-svn: 111022
 2010-08-13 17:50:47 +00:00
Bruno Cardoso Lopes
de5f3f5cb6 Improve comment to make explicit why not to touch this could before JIT goes MC 
llvm-svn: 111021
 2010-08-13 17:44:10 +00:00
Eric Christopher
63c83f19a0 Revert last patch and r110954 as I meant to. 
llvm-svn: 111001
 2010-08-13 02:37:50 +00:00
Eric Christopher
e9a4223bc8 Revert r110954 for now, pseudo instructions can't make it through to the JIT. 
llvm-svn: 111000
 2010-08-13 02:30:00 +00:00
Bruno Cardoso Lopes
350d186d69 Some small clean-up: use of pseudo instructions 
llvm-svn: 110954
 2010-08-12 20:55:18 +00:00
Bruno Cardoso Lopes
7cb26cb8be - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. 
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946
 2010-08-12 20:20:53 +00:00
Bruno Cardoso Lopes
99b5298854 Define AVX 128-bit pattern versions of SET0PS/PD. 
llvm-svn: 110937
 2010-08-12 18:20:59 +00:00
Bruno Cardoso Lopes
43a7ba2bbc Fix comment order 
llvm-svn: 110898
 2010-08-12 02:08:52 +00:00
Bruno Cardoso Lopes
bb491bd56c Begin to support some vector operations for AVX 256-bit intructions. The long 
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897
 2010-08-12 02:06:36 +00:00
Daniel Dunbar
4f45de1b1e MC/X86/AsmParser: Give an explicit error message when we reject an instruction 
because it could have an ambiguous suffix.

llvm-svn: 110890
 2010-08-12 00:55:42 +00:00
Daniel Dunbar
f2b4982344 MC/AsmParser: Push the burdon of emitting diagnostics about unmatched 
instructions onto the target specific parser, which can do a better job.

llvm-svn: 110889
 2010-08-12 00:55:38 +00:00
Daniel Dunbar
0a98bc5619 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888
 2010-08-12 00:55:32 +00:00
Jakob Stoklund Olesen
5a62f10abc Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk. 
When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

llvm-svn: 110874
 2010-08-11 23:08:22 +00:00
Dan Gohman
d91d51116b Use ISD::ADD instead of ISD::SUB with a negated constant. This 
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.

llvm-svn: 110835
 2010-08-11 18:14:00 +00:00
Daniel Dunbar
ee80a239ed MCAsmParser: Add dump() hook to MCParsedAsmOperand. 
llvm-svn: 110790
 2010-08-11 06:37:04 +00:00
Bruno Cardoso Lopes
6eb24fd744 Add AVX matching patterns to Packed Bit Test intrinsics. 
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.

llvm-svn: 110744
 2010-08-10 23:25:42 +00:00
Bruno Cardoso Lopes
f1928b60c0 Add AVX movnt{pd,ps,dq} 256-bit intrinsics 
llvm-svn: 110650
 2010-08-10 02:49:24 +00:00
Bruno Cardoso Lopes
f5884c6791 Add AVX movmsk 256-bit intrinsics 
llvm-svn: 110648
 2010-08-10 02:34:56 +00:00
Bruno Cardoso Lopes
2a7ed4b5c9 Support AVX 256-bit load and store intrinsics 
llvm-svn: 110645
 2010-08-10 01:43:16 +00:00
Bruno Cardoso Lopes
1ea37cfa7b Patterns to match AVX cmp instructions 
llvm-svn: 110633
 2010-08-10 00:13:20 +00:00