Owen Anderson
7a380bac06
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
...
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
Jim Grosbach
6122eb0fff
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
...
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
llvm-svn: 135203
2011-07-14 22:04:21 +00:00
Jim Grosbach
7656c6f97e
Add some testcases for ARM MLA/MLS instructions.
...
llvm-svn: 135196
2011-07-14 21:43:05 +00:00
Jim Grosbach
2ab898973a
ARM MCRR/MCRR2 immediate operand range checking.
...
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
Jim Grosbach
27ebbba831
ARM MCR/MCR2 assembly parsing operand constraints.
...
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
llvm-svn: 135189
2011-07-14 21:19:17 +00:00
Jim Grosbach
09b5985799
Enable some tests we now handle correctly.
...
llvm-svn: 135185
2011-07-14 21:02:23 +00:00
Eric Christopher
ca7ae418a5
Check register class matching instead of width of type matching
...
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.
Fixes PR10352 and rdar://9777108
llvm-svn: 135180
2011-07-14 20:13:52 +00:00
Bruno Cardoso Lopes
d24f039847
Add 256-bit load/store recognition and matching in several places.
...
llvm-svn: 135171
2011-07-14 18:50:58 +00:00
Jim Grosbach
aebb9cdf68
Update ARM Assembly of LDM/STM.
...
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
llvm-svn: 135168
2011-07-14 18:35:38 +00:00
Jim Grosbach
ebbd82a248
ARM ISB assembly parsing tests.
...
llvm-svn: 135158
2011-07-14 18:02:25 +00:00
Jim Grosbach
9bbc2007df
ARM ISB instruction assembly parsing.
...
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
llvm-svn: 135156
2011-07-14 18:00:31 +00:00
Eric Christopher
be21240f6f
Add a testcase for r135123.
...
Part of rdar://9761830
llvm-svn: 135133
2011-07-14 06:23:09 +00:00
Benjamin Kramer
1cab6179ab
Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.
...
llvm-svn: 135126
2011-07-14 01:38:42 +00:00
Jim Grosbach
76bd4e6f75
ARM tests for EOR instruction parsing and encoding.
...
llvm-svn: 135119
2011-07-14 00:22:21 +00:00
Jim Grosbach
fe9c954c0f
Remove duplicate tests.
...
llvm-svn: 135117
2011-07-14 00:19:19 +00:00
Jim Grosbach
4b63d59acb
ARM Assembler support for DSB instruction.
...
Add instalias for default 'sy' option. Add tests.
llvm-svn: 135116
2011-07-14 00:18:13 +00:00
Jim Grosbach
5a96cebd81
ARM Assembler support for DMB instruction.
...
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
llvm-svn: 135109
2011-07-13 23:40:38 +00:00
Jim Grosbach
c0ec4205e2
ARM Assembler support for DBG instruction.
...
Add range checking and testing for parsing and encoding of DBG instruction.
llvm-svn: 135102
2011-07-13 22:59:38 +00:00
Bruno Cardoso Lopes
f29783ee55
We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.
...
llvm-svn: 135099
2011-07-13 22:28:55 +00:00
Jim Grosbach
25a4b8922d
ARM parsing and encoding tests for CMN/CMP.
...
llvm-svn: 135098
2011-07-13 22:26:58 +00:00
Jim Grosbach
d5e74991f0
Shuffle ARM assembly tests a bit.
...
llvm-svn: 135095
2011-07-13 22:19:10 +00:00
Jim Grosbach
fd2ebb4552
Range checking for CDP[2] immediates.
...
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
c0401dddf7
Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
...
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.
llvm-svn: 135088
2011-07-13 21:36:51 +00:00
Eli Friedman
30d557cc28
Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
...
<rdar://problem/9763308>
llvm-svn: 135084
2011-07-13 21:29:53 +00:00
Jim Grosbach
d3b15141b8
Fix predicates for Thumb co-processor instructions.
...
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Jim Grosbach
c7e0941dac
Testcases for ARM assembly BX/BXJ instructions.
...
llvm-svn: 135078
2011-07-13 20:25:46 +00:00
Jim Grosbach
0313701671
Testcases for ARM assembly BLX/BL instructions.
...
llvm-svn: 135072
2011-07-13 20:11:04 +00:00
Jim Grosbach
0caa098513
Range checking for 16-bit immediates in ARM assembly.
...
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Evan Cheng
13c2a2dac3
Change test case, one that actually failed before my commit.
...
llvm-svn: 135064
2011-07-13 19:19:44 +00:00
Jim Grosbach
9e021b5281
Add tests for ARM parsing of 'BKPT' instruction.
...
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach
ce9b6636b3
Fix copy-pasto.
...
llvm-svn: 135062
2011-07-13 19:16:30 +00:00
Jim Grosbach
9d1a4de9e6
Add tests for ARM parsing of 'BIC' instruction.
...
llvm-svn: 135061
2011-07-13 19:12:32 +00:00
Jim Grosbach
7aea4b177f
Add some FIXMEs.
...
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.
llvm-svn: 135060
2011-07-13 19:10:23 +00:00
Evan Cheng
ba4a50f10c
It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is another use of sqrt. rdar://9763193
...
llvm-svn: 135058
2011-07-13 19:08:16 +00:00
Jim Grosbach
9b9604762e
Add tests for ARM parsing of 'AND' instruction.
...
llvm-svn: 135056
2011-07-13 18:55:14 +00:00
Jim Grosbach
5c366bfb36
Improve ARM assembly parsing diagnostics a bit.
...
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.
Add some tests for the diagnostics we do want.
llvm-svn: 135055
2011-07-13 18:49:30 +00:00
Jim Grosbach
a0a947a8ca
Add tests for ARM parsing of 'ADD' instruction
...
llvm-svn: 135053
2011-07-13 18:12:46 +00:00
Jim Grosbach
7dbb39dffa
Destination register operand is optional for ADC and SBC ARM.
...
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach
5db1296fcd
Flesh out ARM Parser support for shifted-register operands.
...
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Bruno Cardoso Lopes
cb49278ad6
AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
...
llvm-svn: 135023
2011-07-13 01:15:33 +00:00
Evan Cheng
37ff73dfaf
Improve codegen for select's:
...
if (x != 0) x = 1
if (x == 1) x = 1
Previous codegen looks like this:
mov r1, r0
cmp r1, #1
mov r0, #0
moveq r0, #1
The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
cmp r0, #1
movne r0, #0
rdar://9758317
llvm-svn: 135017
2011-07-13 00:42:17 +00:00
Jim Grosbach
295e53b228
Add check for predicate w/o S bit.
...
llvm-svn: 134987
2011-07-12 16:25:04 +00:00
Jim Grosbach
863f0216d5
Improve test cases from r134746.
...
Use memory barriers to force if-conversion off for these tests instead of
the internal llc command line option ifcvt-limit.
llvm-svn: 134986
2011-07-12 16:06:01 +00:00
Andrew Trick
a53688c65c
Comment correction.
...
llvm-svn: 134958
2011-07-12 03:39:22 +00:00
Jim Grosbach
fae61bb435
Fix recognition of ARM 'adcs' mnemonic.
...
The 'CS' is not a predication suffix in this case.
llvm-svn: 134903
2011-07-11 17:09:57 +00:00
Jim Grosbach
93f2ebb5e7
Simplify printing of ARM shifted immediates.
...
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
llvm-svn: 134902
2011-07-11 16:48:36 +00:00
NAKAMURA Takumi
183ec41f4a
test/CodeGen/PowerPC/vector.ll: Tweak redirection >%t >%t to >%t >>%t. See also r134814 (test/CodeGen/X86/vector.ll).
...
llvm-svn: 134900
2011-07-11 16:21:52 +00:00
Cameron Zwarich
1efde78890
Add a missing test for r134882.
...
llvm-svn: 134889
2011-07-11 08:35:17 +00:00
Evan Cheng
1346a63a0f
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
...
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Rafael Espindola
b42084315a
Don't duplicate the work done by a gep into a "bitcast" if the gep has
...
more than one use.
Fixes PR10322.
llvm-svn: 134883
2011-07-11 03:43:47 +00:00