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Commit Graph

77377 Commits

Author SHA1 Message Date
Nadav Rotem
dad9eeadbb Fix a typo.w
llvm-svn: 142729
2011-10-22 18:44:51 +00:00
Jim Grosbach
b10647b119 Minor updates.
llvm-svn: 142728
2011-10-22 18:17:32 +00:00
Nadav Rotem
c5c37861f7 Added my name to CREDITS.TXT
llvm-svn: 142727
2011-10-22 17:51:04 +00:00
Benjamin Kramer
03065133c3 Move various generated tables into read-only memory, fixing up const correctness along the way.
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
Nadav Rotem
7a79f94aad Fix pr11193.
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.

llvm-svn: 142724
2011-10-22 12:39:25 +00:00
Bill Wendling
66327a8d0e The different flavors of ARM have different valid subsets of registers. Check
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2

llvm-svn: 142706
2011-10-22 00:29:28 +00:00
Jim Grosbach
d964cf8939 Assembly parsing for 4-register sequential variant of VLD2.
llvm-svn: 142704
2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2.
llvm-svn: 142691
2011-10-21 22:21:10 +00:00
Bill Wendling
34a9073d67 Make sure that the landing pads themselves have no PHI instructions in them.
The assumption in the back-end is that PHIs are not allowed at the start of the
landing pad block for SjLj exceptions.
<rdar://problem/10313708>

llvm-svn: 142689
2011-10-21 22:08:56 +00:00
Benjamin Kramer
917737037d Extend the floating point heuristic to consider NaN checks unlikely.
llvm-svn: 142687
2011-10-21 21:13:47 +00:00
Tanya Lattner
84bb012d55 Revert r141657 for now. This has broken css and changed links on llvm.org. I'd like to understand exactly why the links have changed and if a newer doxygen is required. This may be reapplied once we upgrade on llvm.org and it is fully tested.
llvm-svn: 142686
2011-10-21 20:51:54 +00:00
Eli Friedman
5012ac7cc0 Remap blockaddress correctly when inlining a function. Fixes PR10162.
llvm-svn: 142684
2011-10-21 20:45:19 +00:00
Owen Anderson
0d40d283e9 Use LLVMBool for a function that logically returns a boolean value.
llvm-svn: 142683
2011-10-21 20:35:58 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1.
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
Owen Anderson
7faa1c3317 Fix typo.
llvm-svn: 142681
2011-10-21 20:28:19 +00:00
Benjamin Kramer
66a199d42f BranchProbabilityInfo: floating point equality is unlikely.
This is from the same paper from Ball and Larus as the rest of the currently implemented heuristics.

llvm-svn: 142677
2011-10-21 20:12:47 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1.
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
Owen Anderson
806a1e5c78 STABS symbols are debug symbols.
llvm-svn: 142673
2011-10-21 19:26:54 +00:00
Eli Friedman
28f3ff0d3d Minor simplification: use ShuffleVectorInst::getMaskValue instead of a more expensive helper.
llvm-svn: 142672
2011-10-21 19:11:34 +00:00
Eli Friedman
fb0b9216e1 Extend instcombine's shufflevector simplification to handle more cases where the input and output vectors have different sizes. Patch by Xiaoyi Guo.
llvm-svn: 142671
2011-10-21 19:06:29 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
2011-10-21 18:54:25 +00:00
Owen Anderson
ccc76e17cc Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
llvm-svn: 142669
2011-10-21 18:43:28 +00:00
Owen Anderson
da28398bb6 Bind libObject API for obtaining the section containing a Symbol.
llvm-svn: 142667
2011-10-21 18:21:22 +00:00
Owen Anderson
33b5868dab Expand the coverage of the libObject C bindings to include more SectionRef accessors as well as Symbol iterators.
llvm-svn: 142661
2011-10-21 17:50:59 +00:00
Nadav Rotem
57f652cfe4 Fix pr11194. When promoting and splitting integers we need to use
ZExtPromotedInteger and SExtPromotedInteger based on the operation we legalize.

SetCC return type needs to be legalized via PromoteTargetBoolean.

llvm-svn: 142660
2011-10-21 17:35:19 +00:00
Jim Grosbach
9b539fab9d Nuke an #if0 that got accidentally left in.
llvm-svn: 142658
2011-10-21 16:59:08 +00:00
Jim Grosbach
a1d54f2c7a whitespace.
llvm-svn: 142657
2011-10-21 16:56:40 +00:00
Chandler Carruth
2f20f63a01 Don't hard code the desired alignment for loops -- it isn't 16-bytes on
all x86 systems. Sorry for the breakage.

llvm-svn: 142656
2011-10-21 16:41:39 +00:00
Jim Grosbach
501c72cdc5 Remove some outdated comments.
llvm-svn: 142653
2011-10-21 16:14:12 +00:00
Nadav Rotem
52d820c0dd 1. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC type.
2. Fix a typo in CONCAT_VECTORS which exposed the bug in #1.

llvm-svn: 142648
2011-10-21 11:42:07 +00:00
Duncan Sands
926a63ed67 Ensure timestamps are not embedded into files when doing a release build.
llvm-svn: 142647
2011-10-21 09:47:14 +00:00
Anton Korobeynikov
e91e40b137 Fix build on mingw-w64.
Patch by Ruben Van Boxem!

llvm-svn: 142646
2011-10-21 09:38:50 +00:00
Chandler Carruth
21c689d1ac Add loop aligning to MachineBlockPlacement based on review discussion so
it's a bit more plausible to use this instead of CodePlacementOpt. The
code for this was shamelessly stolen from CodePlacementOpt, and then
trimmed down a bit. There doesn't seem to be much utility in returning
true/false from this pass as we may or may not have rewritten all of the
blocks. Also, the statistic of counting how many loops were aligned
doesn't seem terribly important so I removed it. If folks would like it
to be included, I'm happy to add it back.

This was probably the most egregious of the missing features, and now
I'm going to start gathering some performance numbers and looking at
specific loop structures that have different layout between the two.

Test is updated to include both basic loop alignment and nested loop
alignment.

llvm-svn: 142645
2011-10-21 08:57:37 +00:00
Chandler Carruth
f352d2d7e3 Add a very basic test for MachineBlockPlacement. This is essentially the
canonical example I used when developing it, and is one of the primary
motivating real-world use cases for __builtin_expect (when burried under
a macro).

I'm working on more test cases here, but I'm trying to make sure both
that the pass is doing the right thing with the test cases and that they
aren't too brittle to changes elsewhere in the code generation pipeline.

Feedback and/or suggestions on how to test this are very welcome.
Especially feedback on whether testing the block comments is a good
strategy; I couldn't find any good examples to steal from but all the
other ideas I had were a lot uglier or more fragile.

llvm-svn: 142644
2011-10-21 08:01:56 +00:00
Bill Wendling
7956e709bf Modify the script to output the regressions and passes into categories. My Python-fu could use some improving...
llvm-svn: 142643
2011-10-21 06:58:01 +00:00
Craig Topper
fd96157f13 Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.
llvm-svn: 142642
2011-10-21 06:55:01 +00:00
Chandler Carruth
380e0d5013 Implement a block placement pass based on the branch probability and
block frequency analyses. This differs substantially from the existing
block-placement pass in LLVM:

1) It operates on the Machine-IR in the CodeGen layer. This exposes much
   more (and more precise) information and opportunities. Also, the
   results are more stable due to fewer transforms ocurring after the
   pass runs.
2) It uses the generalized probability and frequency analyses. These can
   model static heuristics, code annotation derived heuristics as well
   as eventual profile loading. By basing the optimization on the
   analysis interface it can work from any (or a combination) of these
   inputs.
3) It uses a more aggressive algorithm, both building chains from tho
   bottom up to maximize benefit, and using an SCC-based walk to layout
   chains of blocks in a profitable ordering without O(N^2) iterations
   which the old pass involves.

The pass is currently gated behind a flag, and not enabled by default
because it still needs to grow some important features. Most notably, it
needs to support loop aligning and careful layout of loop structures
much as done by hand currently in CodePlacementOpt. Once it supports
these, and has sufficient testing and quality tuning, it should replace
both of these passes.

Thanks to Nick Lewycky and Richard Smith for help authoring & debugging
this, and to Jakob, Andy, Eric, Jim, and probably a few others I'm
forgetting for reviewing and answering all my questions. Writing
a backend pass is *sooo* much better now than it used to be. =D

llvm-svn: 142641
2011-10-21 06:46:38 +00:00
Bill Wendling
e9d5765aba Check for divide by zero.
llvm-svn: 142640
2011-10-21 06:26:01 +00:00
Chandler Carruth
2d28407280 Remove a now dead function, fixing -Wunused-function warnings from
Clang.

llvm-svn: 142631
2011-10-21 01:23:41 +00:00
Richard Smith
80f49e9eaa Fix unused variable warning.
llvm-svn: 142630
2011-10-21 01:22:04 +00:00
Owen Anderson
2021ad2133 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
Owen Anderson
8067075218 Fix decoding tests for fixed MSR encodings.
llvm-svn: 142624
2011-10-20 22:01:48 +00:00
David Meyer
fd278b1f98 Remove unused include of sys/uio.h in MemoryBuffer.cpp. It was not correctly protected by ifdef either.
llvm-svn: 142623
2011-10-20 21:57:46 +00:00
Owen Anderson
ffca195c01 Fix tests for corrected MSR encodings.
llvm-svn: 142622
2011-10-20 21:53:19 +00:00
Dan Gohman
5b37d690b5 Disable the PPC hazard recognizer. It currently only supports
top-down scheduling and top-down scheduling is going away.

llvm-svn: 142621
2011-10-20 21:45:36 +00:00
Dan Gohman
666f749afc Delete the list-tdrr scheduler. Top-down schedulers are going away
because they don't support physical register dependencies.

llvm-svn: 142620
2011-10-20 21:44:34 +00:00
Owen Anderson
24f04143bc Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
llvm-svn: 142618
2011-10-20 21:24:38 +00:00
Bill Wendling
3e34fd8604 Add missing operand. <rdar://problem/10313323>
llvm-svn: 142615
2011-10-20 20:37:11 +00:00
Duncan Sands
b3278272ae Also compare the built dragonegg objects between phases 2 and 3.
llvm-svn: 142608
2011-10-20 20:14:18 +00:00
Duncan Sands
c52861c44e Reset the system compiler each time we start a new flavour. Otherwise
the last compiler built for the previous flavour is used for the next,
for example the Debug clang compiler was being used for the initial build
of the Release LLVM.  Flavors should be independent of each other.  This
especially matters if the compiler built for the previous flavour doesn't
actually work!

llvm-svn: 142607
2011-10-20 20:10:58 +00:00