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73 Commits

Author SHA1 Message Date
Johnny Chen
346e6b6cac Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not 
fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.

llvm-svn: 89377
 2009-11-19 19:20:17 +00:00
Anton Korobeynikov
ed410a8ee3 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Anton Korobeynikov
3ba3789153 Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) 
llvm-svn: 85764
 2009-11-02 00:10:38 +00:00
Bob Wilson
ace97183c7 Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.

llvm-svn: 85169
 2009-10-26 22:42:13 +00:00
Bob Wilson
e85a3142bc Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730
 2009-10-21 02:15:46 +00:00
Jim Grosbach
ea7293494f Refs: A8-598. 
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.

llvm-svn: 84572
 2009-10-20 00:38:19 +00:00
Jim Grosbach
aaa0e97800 Add missing encoding bits to NLdSt class of instructions. 
Patch by Johnny Chen.

llvm-svn: 84570
 2009-10-20 00:19:08 +00:00
Bob Wilson
e7173601a3 Add some instruction encoding bits for NEON load/store instructions. 
llvm-svn: 83490
 2009-10-07 21:53:04 +00:00
Evan Cheng
54a1a87862 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo 
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982
 2009-09-28 09:14:39 +00:00
Evan Cheng
7f25e554e4 Fix double load / store multiple encoding. 
llvm-svn: 81403
 2009-09-09 23:55:03 +00:00
Bob Wilson
d4fbf1f70a Expose the instruction contraint string as an argument to the NLdSt class. 
llvm-svn: 80011
 2009-08-25 17:46:06 +00:00
David Goodwin
36a5b02e4f Use NEON for single-precision int<->FP conversions. 
llvm-svn: 78604
 2009-08-10 22:17:39 +00:00
Anton Korobeynikov
ae22c37afb Use VLDM / VSTM to spill/reload 128-bit Neon registers 
llvm-svn: 78468
 2009-08-08 13:35:48 +00:00
David Goodwin
3aafcc1dd2 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
Evan Cheng
e366789b50 Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
llvm-svn: 78126
 2009-08-04 23:47:55 +00:00
David Goodwin
648590849c Add NEON single-precision FP support for fabs and fneg. 
llvm-svn: 78101
 2009-08-04 20:39:05 +00:00
David Goodwin
99adffe5f2 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
David Goodwin
6ff3fd8021 Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2). 
llvm-svn: 77242
 2009-07-27 19:59:26 +00:00
David Goodwin
6fa63db9be Fix typo in addrmode definition. 
llvm-svn: 76806
 2009-07-22 22:24:31 +00:00
Evan Cheng
268b47b1fb Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
 2009-07-11 06:43:01 +00:00
David Goodwin
1a6f4f6f8d Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2. 
llvm-svn: 75254
 2009-07-10 17:03:29 +00:00
Evan Cheng
991f885915 - Add some NEON ld / st instruction static encoding. 
- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.

llvm-svn: 75065
 2009-07-08 22:51:32 +00:00
Bob Wilson
3809b333de Implement NEON vld1 instructions. 
llvm-svn: 75019
 2009-07-08 18:11:30 +00:00
Evan Cheng
18d70ca551 Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant. 
llvm-svn: 74988
 2009-07-08 01:46:35 +00:00
Evan Cheng
dad6a41d14 Thumb2 pre/post indexed loads. 
llvm-svn: 74696
 2009-07-02 07:28:31 +00:00
Evan Cheng
57bb186a0c Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate. 
llvm-svn: 74692
 2009-07-02 06:38:40 +00:00
Bob Wilson
810a970c6f Add a new addressing mode for NEON load/store instructions. 
llvm-svn: 74658
 2009-07-01 23:16:05 +00:00
David Goodwin
5545d82866 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. 
llvm-svn: 74543
 2009-06-30 18:04:13 +00:00
Evan Cheng
2a527c3419 A few more load instructions. 
llvm-svn: 74500
 2009-06-30 02:15:48 +00:00
Evan Cheng
093adf3ff9 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
 2009-06-29 07:51:04 +00:00
Evan Cheng
817712377a Renaming for consistency. 
llvm-svn: 74368
 2009-06-27 02:26:13 +00:00
Evan Cheng
a3be8cba60 Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag. 
llvm-svn: 74158
 2009-06-25 02:08:06 +00:00
Evan Cheng
1333ee8eb6 Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available. 
llvm-svn: 73985
 2009-06-23 19:38:13 +00:00
Evan Cheng
3e8033f7f7 Initial Thumb2 support. Majority of the work is done by David Goodwin. There are 
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.

I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.

Test cases will be contributed later after I re-organize what's in svn first.

llvm-svn: 73965
 2009-06-23 17:48:47 +00:00
Bob Wilson
6db76aaf10 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
 2009-06-22 23:27:02 +00:00
Evan Cheng
f7c1da41a1 Handle the rest of pseudo instructions. 
llvm-svn: 59275
 2008-11-13 23:36:57 +00:00
Evan Cheng
3c0113820b Fix pre- and post-indexed load / store encoding bugs. 
llvm-svn: 59230
 2008-11-13 07:34:59 +00:00
Evan Cheng
7fef8cfe75 Consolidate formats; fix FCMPED etc. encodings. 
llvm-svn: 59107
 2008-11-12 07:18:38 +00:00
Evan Cheng
0966883093 Fix VFP conversion instruction encodings. 
llvm-svn: 59104
 2008-11-12 06:41:41 +00:00
Evan Cheng
8b7fefc126 Fix FMDRR encoding. 
llvm-svn: 59088
 2008-11-11 22:46:12 +00:00
Evan Cheng
35f1477c5a Encode VFP load / store instructions. 
llvm-svn: 59084
 2008-11-11 21:48:44 +00:00
Evan Cheng
91e4ef91c5 Encode VFP conversion instructions. 
llvm-svn: 59074
 2008-11-11 19:40:26 +00:00
Evan Cheng
3c62bb7471 Encode VFP arithmetic instructions. 
llvm-svn: 59016
 2008-11-11 02:11:05 +00:00
Evan Cheng
21df9f3b4f Jump table JIT support. Work in progress. 
llvm-svn: 58836
 2008-11-07 09:06:08 +00:00
Evan Cheng
88726d85eb Encode misc arithmetic instructions. 
llvm-svn: 58828
 2008-11-07 01:41:35 +00:00
Evan Cheng
3bcb71912f Encode extend instructions; more clean up. 
llvm-svn: 58818
 2008-11-06 22:15:19 +00:00
Evan Cheng
af54e4ed18 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
 2008-11-06 17:48:05 +00:00
Evan Cheng
aa24d19533 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Evan Cheng
078361bddc Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>. 
llvm-svn: 58793
 2008-11-06 03:35:07 +00:00