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7478 Commits

Author SHA1 Message Date
Eli Friedman
7bb0485237 PR4662: Fix a crash introduced by the recent LLVMContext changes. 
llvm-svn: 77716
 2009-07-31 19:36:47 +00:00
Chris Lattner
75b7692e66 switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.

llvm-svn: 77708
 2009-07-31 18:48:30 +00:00
Evan Cheng
0c9705feed Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.

llvm-svn: 77705
 2009-07-31 18:35:56 +00:00
Chris Lattner
85a3632c7a fix PR4650: we only track sizes for certain objects, so only put something 
into the mergable section if it is one of our special cases.  This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.

llvm-svn: 77679
 2009-07-31 16:17:13 +00:00
Daniel Dunbar
813b35a4b7 Add this test back, the check pattern was too strict. 
llvm-svn: 77662
 2009-07-31 03:11:49 +00:00
Daniel Dunbar
ed28c20ca7 Remove this test while I figure out why it is failing. 
llvm-svn: 77659
 2009-07-31 02:46:36 +00:00
Daniel Dunbar
41639473ed llvm-mc: Match a few X86 instructions. 
- This is "experimental" code, I am feeling my way around and working out the
   best way to do things (and learning tblgen in the process). Comments welcome,
   but keep in mind this stuff will change radically.

 - This is enough to match "subb" and friends, but not much else. The next step is to
   automatically generate the matchers for individual operands.

llvm-svn: 77657
 2009-07-31 02:32:59 +00:00
Evan Cheng
c9f31ae969 When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
llvm-svn: 77642
 2009-07-30 23:29:25 +00:00
Devang Patel
c3f4aa73cc Do not use abbrev while writing NamedMDNode name. 
llvm-svn: 77637
 2009-07-30 23:06:35 +00:00
David Goodwin
62efc71b9f Darwin assembler now recognizes "orn", so remove workaround. 
llvm-svn: 77627
 2009-07-30 21:51:41 +00:00
David Goodwin
d29f81da16 Darwin assembler now supports "rrx", so remove workaround. 
llvm-svn: 77625
 2009-07-30 21:38:40 +00:00
David Goodwin
2eaffa79af Cleanup and include code selection for some frame index cases. 
llvm-svn: 77622
 2009-07-30 18:56:48 +00:00
Evan Cheng
148032a1a2 Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582
 2009-07-30 08:33:02 +00:00
Dan Gohman
3c7e8160f6 Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565
 2009-07-30 01:56:29 +00:00
Evan Cheng
31ac181755 tbb / tbh instructions only branch forward, not backwards. 
llvm-svn: 77522
 2009-07-29 23:20:20 +00:00
Evan Cheng
fabbd6219a Add VFP3 D registers to the DPR register class. 
llvm-svn: 77521
 2009-07-29 23:03:41 +00:00
Devang Patel
d5b7c64109 Read and write NamedMDNode. 
llvm-svn: 77517
 2009-07-29 22:34:41 +00:00
Daniel Dunbar
89cb72a6bc Fix PR4645 which was fallout from the fix for PR4641. 
- Call RAUW to delete all instructions (this is a patch from Nick Lewycky).

llvm-svn: 77512
 2009-07-29 22:00:43 +00:00
Evan Cheng
9712360f80 xfail for now. 
llvm-svn: 77478
 2009-07-29 17:40:28 +00:00
Bob Wilson
355e0b70e0 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.

llvm-svn: 77468
 2009-07-29 16:39:22 +00:00
Nick Lewycky
1961298b63 Just discard the output, no need to turn it back into text. 
llvm-svn: 77439
 2009-07-29 06:14:52 +00:00
Chris Lattner
e5f1099d05 don't dump .bc file to stdout, and simplify this to a trivial testcase. 
llvm-svn: 77436
 2009-07-29 05:32:07 +00:00
Chris Lattner
f8a9c2f843 fix PR4584 with a trivial patch now that the pieces are in place. 
llvm-svn: 77434
 2009-07-29 05:20:33 +00:00
Nick Lewycky
e0524c1795 Bulk erasing instructions without RAUWing them is unsafe. Instead, break them 
into a new BB that has no predecessors.

llvm-svn: 77433
 2009-07-29 05:17:50 +00:00
Evan Cheng
fc846dd401 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
Eric Christopher
88c1b51020 Add a couple more tests for the ptest intrinsics to make sure we're 
grabbing them all correctly.

llvm-svn: 77413
 2009-07-29 00:51:15 +00:00
Eric Christopher
c7b97d1f03 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.

llvm-svn: 77407
 2009-07-29 00:28:05 +00:00
Andreas Bolka
7d6b4c24e6 Slightly reformat LDA tests to ease grepping. 
llvm-svn: 77398
 2009-07-28 23:40:40 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin
0c9e96bf09 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
David Goodwin
dbc23ece04 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
Chris Lattner
a8faf6b1b6 fix testcase for previous patch. 
llvm-svn: 77338
 2009-07-28 18:04:18 +00:00
Chris Lattner
986bd2bd0a Fix PR4639, a ELF-TLS regression from some of my refactoring. 
llvm-svn: 77336
 2009-07-28 17:57:51 +00:00
David Goodwin
e94d490b89 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng
05555a7d31 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
llvm-svn: 77305
 2009-07-28 07:38:35 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
Dan Gohman
0d0dd7b732 Teach instcombine to respect and preserve inbounds. Add inbounds 
to a few tests where it is required for the expected transformation.

llvm-svn: 77290
 2009-07-28 01:40:03 +00:00
David Goodwin
0bcb94eeff ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
Daniel Dunbar
3edfc4bb16 llvm-mc: Implement .abort fully in the front end 
llvm-svn: 77272
 2009-07-27 23:20:52 +00:00
Dan Gohman
490eb36e1d Add a new keyword 'inbounds' for use with getelementptr. See the 
LangRef.html changes for details.

llvm-svn: 77259
 2009-07-27 21:53:46 +00:00
David Goodwin
471e9f5b8d Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Sanjiv Gupta
f39c96217b Test case to check that separate section is created for a global variable specified with section attribute. 
llvm-svn: 77195
 2009-07-27 16:20:41 +00:00
Dan Gohman
39c0d3b10a Change the assembly syntax for nsw, nuw, and exact, putting them 
after their associated opcodes rather than before. This makes them
a little easier to read.

llvm-svn: 77194
 2009-07-27 16:11:46 +00:00
Chris Lattner
19c9914343 update testcase. 
llvm-svn: 77192
 2009-07-27 15:52:58 +00:00
Chris Lattner
5547fd80ad put normal data into .data instead of .data.rel on elf systems. 
llvm-svn: 77116
 2009-07-26 03:06:11 +00:00
Chris Lattner
9cd489c7f1 finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal 
for now.  Make the section switching directives more consistent
by not including \n and including \t for them all.

llvm-svn: 77107
 2009-07-26 01:24:18 +00:00
Chris Lattner
b95150b65a simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bit 
and make it more aggressive, we now put:

const int G2 __attribute__((weak)) = 42;

into the text (readonly) segment like gcc, previously we put
it into the data (readwrite) segment.

llvm-svn: 77104
 2009-07-26 00:51:36 +00:00
Bob Wilson
ec256c8938 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.

llvm-svn: 77101
 2009-07-26 00:39:34 +00:00
Chris Lattner
cf7cc0ed7d add the most expedient hack to fix PR4619, along with a testcase. 
Thanks to Rafael for the great example.

llvm-svn: 77083
 2009-07-25 17:57:37 +00:00
Dan Gohman
c126330ef1 When attempting to sign-extend an addrec by interpreting 
the step value as unsigned, the start value and the addrec
itself still need to be treated as signed.

llvm-svn: 77078
 2009-07-25 16:03:30 +00:00