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32 Commits

Author SHA1 Message Date
Colin LeMahieu
d875c88104 [Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding. 
The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes.

Another way is to put a .word32 and mix code and data within a function.  The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware.

This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits.  Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register.

llvm-svn: 261006
 2016-02-16 20:38:17 +00:00
Colin LeMahieu
350f96d137 [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission. 
llvm-svn: 252443
 2015-11-09 04:07:48 +00:00
Krzysztof Parzyszek
68328f0930 [Hexagon] Remove the remnants of isConstExtProfitable 
llvm-svn: 250845
 2015-10-20 19:04:53 +00:00
Colin LeMahieu
fa53018d3f [Hexagon] Adding skeleton of HVX extension instructions. 
llvm-svn: 250600
 2015-10-17 01:33:04 +00:00
Colin LeMahieu
68ef17e4c2 [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width. 
llvm-svn: 239634
 2015-06-12 19:57:32 +00:00
Colin LeMahieu
705d770c5e [Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly. 
llvm-svn: 239477
 2015-06-10 16:52:32 +00:00
Colin LeMahieu
b9726af751 [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing. 
llvm-svn: 239161
 2015-06-05 16:00:11 +00:00
Colin LeMahieu
b1cfdef068 Revert r239095 incorrect test tree. 
llvm-svn: 239102
 2015-06-04 21:32:42 +00:00
Colin LeMahieu
cdf9553102 [Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. 
llvm-svn: 239095
 2015-06-04 21:16:16 +00:00
Brendon Cahoon
37b8b0d293 [Hexagon] Use constant extenders to fix up hardware loops 
Use a loop instruction with a constant extender for a hardware
loop instruction that is too far away from the start of the loop.
This is cheaper than changing the SA register value.

Differential Revision: http://reviews.llvm.org/D9262

llvm-svn: 235882
 2015-04-27 14:16:43 +00:00
Krzysztof Parzyszek
49d1e29261 Remove unused complex patterns for addressing modes on Hexagon. 
llvm-svn: 232057
 2015-03-12 16:44:50 +00:00
Krzysztof Parzyszek
62f208b598 Eliminate constant-extender profitability checks from Hexagon isel 
llvm-svn: 231992
 2015-03-12 00:19:59 +00:00
Colin LeMahieu
6ba6e9c428 [Hexagon] Removing more V4 predicates since V4 is the required minimum. 
llvm-svn: 228614
 2015-02-09 21:56:37 +00:00
Colin LeMahieu
90f37476de [Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms. 
llvm-svn: 228220
 2015-02-04 22:36:28 +00:00
Colin LeMahieu
6a07b73882 [Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them. 
llvm-svn: 228184
 2015-02-04 20:38:01 +00:00
Eric Christopher
5cb620ce06 Migrate HexagonISelDAGToDAG to setting a subtarget pointer during 
runOnMachineFunction. Update all uses of the Subtarget accordingly.

llvm-svn: 227840
 2015-02-02 19:22:03 +00:00
Colin LeMahieu
159f2e1618 [Hexagon] Deleting a lot of old variants of intrinsics and updating references. 
llvm-svn: 227338
 2015-01-28 18:29:11 +00:00
Colin LeMahieu
c9d3d690e7 [Hexagon] Converting remaining ALU32/ALU intrinsics. 
llvm-svn: 226480
 2015-01-19 18:33:58 +00:00
Colin LeMahieu
e59b0ff43e [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch. 
llvm-svn: 225283
 2015-01-06 19:03:20 +00:00
Colin LeMahieu
7c1bcabc22 [Hexagon] Adding dealloc_return encoding and absolute address stores. 
llvm-svn: 225267
 2015-01-06 16:15:15 +00:00
Colin LeMahieu
c88fff49c9 [Hexagon] Adding classes and load unsigned byte instruction, updating usages. 
llvm-svn: 224730
 2014-12-22 21:20:03 +00:00
Colin LeMahieu
4c0e2a35a6 [Hexagon] Adding doubleword multiplies with and without accumulation. 
llvm-svn: 224293
 2014-12-16 00:07:24 +00:00
Jyotsna Verma
2878599f9d Move all operand definitions into HexagonOperands.td 
llvm-svn: 169213
 2012-12-04 05:00:31 +00:00
Jyotsna Verma
a762d2c7c0 Define unsigned const-ext predicates. 
llvm-svn: 169149
 2012-12-03 20:39:45 +00:00
Jyotsna Verma
c9aa3a1e1b Removing unnecessary 'else' statement from the predicates defined in HexagonOperards.td. 
llvm-svn: 169148
 2012-12-03 20:14:38 +00:00
Jyotsna Verma
deb06efce6 Define signed const-ext predicates. 
llvm-svn: 169117
 2012-12-03 06:54:50 +00:00
Jyotsna Verma
f5ca442d79 Define signed const-ext immediate operands and their predicates. 
llvm-svn: 168810
 2012-11-28 20:58:14 +00:00
Jyotsna Verma
cac9f4bdf8 Fix comments in HexagonOperands.td. 
llvm-svn: 168617
 2012-11-26 21:56:51 +00:00
Jyotsna Verma
57c7894ac6 Add new predicates for the immediate operands. 
llvm-svn: 168451
 2012-11-21 20:05:09 +00:00
Jyotsna Verma
ccd944029e Use one common 'let' expression to set PrintMethod for all immediate operands. 
llvm-svn: 168449
 2012-11-21 19:53:42 +00:00
Rafael Espindola
eeea053b3e Finish the renaming. 
llvm-svn: 168437
 2012-11-21 16:56:33 +00:00
Jyotsna Verma
79da647716 Renamed HexagonImmediates.td -> HexagonOperands.td. 
llvm-svn: 168434
 2012-11-21 16:28:18 +00:00