Eli Friedman
802dd20495
Atomic load/store on ARM/Thumb.
...
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
Bruno Cardoso Lopes
e6119d18de
Do the same as r138461. Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138592
2011-08-25 22:23:58 +00:00
Nick Lewycky
59cb9e0d85
Remove stray fullstop.
...
llvm-svn: 138589
2011-08-25 21:46:20 +00:00
Bruno Cardoso Lopes
5b3d2c9e17
Add support for AVX 256-bit version of MOVDDUP!
...
llvm-svn: 138588
2011-08-25 21:40:37 +00:00
Bruno Cardoso Lopes
dedd2ffa0b
Make isMOVDDUP mask check more strict and update comments!
...
llvm-svn: 138587
2011-08-25 21:40:34 +00:00
Owen Anderson
d387b48b0b
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
Andrew Trick
0dd0ae11f8
ARM fix for missing implicit operands on ldmia_ret.
...
rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
Andrew Trick
cd6126c2ab
whitespace
...
llvm-svn: 138566
2011-08-25 17:40:54 +00:00
Jim Grosbach
e8641a3bc7
Explicitly disallow predication in Thumb1 assembly.
...
llvm-svn: 138562
2011-08-25 17:23:55 +00:00
Craig Topper
a6085b9757
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
...
llvm-svn: 138553
2011-08-25 08:11:01 +00:00
Craig Topper
06ed6cb856
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
...
llvm-svn: 138551
2011-08-25 06:57:46 +00:00
Bruno Cardoso Lopes
5d34219953
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
...
llvm-svn: 138546
2011-08-25 02:58:26 +00:00
Bruno Cardoso Lopes
ccffe56b5d
Add memory version of SHUFPD to mask decoding!
...
llvm-svn: 138545
2011-08-25 02:58:21 +00:00
Evan Cheng
7de8defb9c
Hide -global-merge option.
...
llvm-svn: 138540
2011-08-25 01:22:49 +00:00
Evan Cheng
6c89acc6d1
Add a command line option to disable global merge pass.
...
llvm-svn: 138536
2011-08-25 01:00:36 +00:00
Evan Cheng
9a2607f3b9
Remove a out-of-place comment.
...
llvm-svn: 138534
2011-08-25 00:54:42 +00:00
Bruno Cardoso Lopes
dfa5cf4620
Create a section for non-instructions patterns in the beginning of the
...
file, and move more code around!
llvm-svn: 138521
2011-08-24 23:18:11 +00:00
Bruno Cardoso Lopes
719b357628
Move code around!
...
llvm-svn: 138520
2011-08-24 23:18:09 +00:00
Bruno Cardoso Lopes
3824b766ac
Organize UNPCK* patterns, also add remaining for AVX.
...
llvm-svn: 138519
2011-08-24 23:18:06 +00:00
Bruno Cardoso Lopes
82c8bc7efd
Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate
...
the missing ones for AVX.
llvm-svn: 138518
2011-08-24 23:18:04 +00:00
Bruno Cardoso Lopes
d315a6b6e6
Organize and tidy up MOVDDUP section. Also update comments!
...
llvm-svn: 138517
2011-08-24 23:18:02 +00:00
Bruno Cardoso Lopes
762fb13cc9
Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the
...
pattern for 128-bit AVX mode.
llvm-svn: 138516
2011-08-24 23:17:59 +00:00
Bruno Cardoso Lopes
d62766849f
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!
llvm-svn: 138515
2011-08-24 23:17:57 +00:00
Bruno Cardoso Lopes
122f7cfc92
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
llvm-svn: 138514
2011-08-24 23:17:55 +00:00
Owen Anderson
8a6cf48f0e
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
Eli Friedman
b6597a2e70
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
...
llvm-svn: 138505
2011-08-24 22:33:28 +00:00
Jim Grosbach
76b50c3819
ARM asm backend initialize isThumbMode based on target triple.
...
llvm-svn: 138501
2011-08-24 22:27:35 +00:00
Jim Grosbach
7374e16344
Thumb .n mnemonic qualifiers can be ignored for now.
...
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
Jim Grosbach
effaf1e15d
Thumb parsing and encoding for SUB (SP minu immediate).
...
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
Owen Anderson
3732f1644b
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
Jim Grosbach
b2b155a93f
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
Eli Friedman
e4cd816e7b
Fix whitespace.
...
llvm-svn: 138487
2011-08-24 21:17:30 +00:00
Eli Friedman
6f95a6ae1b
Basic x86 code generation for atomic load and store instructions.
...
llvm-svn: 138478
2011-08-24 20:50:09 +00:00
Jim Grosbach
ccee1ff0f5
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
...
rdar://10015134
llvm-svn: 138467
2011-08-24 20:06:14 +00:00
Bruno Cardoso Lopes
734febce18
Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138461
2011-08-24 18:48:33 +00:00
Jim Grosbach
9ae0de4db3
Add missing explicit writeback operand to tSTMIA_UPD.
...
rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
Evan Cheng
420bf5446c
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
Jim Grosbach
bf012c3f19
Thumb add SP assembly syntax fix.
...
llvm-svn: 138448
2011-08-24 18:04:27 +00:00
Jim Grosbach
b33129ebad
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
...
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
Owen Anderson
ee4d781cd3
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
Richard Osborne
6b6b0b535d
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
...
variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
Craig Topper
1da38a34a6
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
...
llvm-svn: 138427
2011-08-24 06:14:18 +00:00
Bruno Cardoso Lopes
8959b54713
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
...
permutations. Also tidy up some patterns and make them close to their
instruction definition!
llvm-svn: 138392
2011-08-23 22:06:37 +00:00
Jim Grosbach
b65ec7c64f
Move ARM frame-unwinding EHABI handling a touch earlier.
...
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
Jim Grosbach
3832c5ac34
[SU]XT[BH] are only available on ARMv6 and up.
...
llvm-svn: 138373
2011-08-23 20:53:08 +00:00
Evan Cheng
ed13551c1d
Some refactoring so TargetRegistry.h no longer has to include any files
...
from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
Jim Grosbach
1f5b8e9044
Thumb parsing and encoding for SVC.
...
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
Nick Lewycky
11874a4e0a
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
...
llvm-svn: 138354
2011-08-23 19:01:24 +00:00
Jim Grosbach
f9bc99b518
Thumb parsing and encoding for tSTRspi.
...
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
Jim Grosbach
3b20e779cd
Thumb parsing and encoding for STM.
...
llvm-svn: 138345
2011-08-23 18:15:37 +00:00