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590 Commits

Author SHA1 Message Date
Chris Lattner
8193d4af33 remove attribution from lib Makefiles. 
llvm-svn: 45415
 2007-12-29 20:09:26 +00:00
Evan Cheng
64a1febf9a Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Evan Cheng
fdd03d0589 Doh 
llvm-svn: 44694
 2007-12-08 01:01:07 +00:00
Evan Cheng
28c2b7e647 Fix a compilation warning. 
llvm-svn: 44692
 2007-12-08 01:00:31 +00:00
Evan Cheng
8464a0bf00 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether 
the stored register is killed.

llvm-svn: 44600
 2007-12-05 03:14:33 +00:00
Evan Cheng
58b387dfb0 Remove redundant foldMemoryOperand variants and other code clean up. 
llvm-svn: 44517
 2007-12-02 08:30:39 +00:00
Evan Cheng
79e8b92dc3 Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0. 
llvm-svn: 44479
 2007-12-01 02:07:52 +00:00
Chris Lattner
706eb604ae several entries got significantly better, though they still aren't done. 
llvm-svn: 44382
 2007-11-27 22:41:52 +00:00
Chris Lattner
d2ee2dad04 implement a trivial readme entry. 
llvm-svn: 44380
 2007-11-27 22:36:16 +00:00
Chris Lattner
28262fbaf2 Several changes: 
1) Change the interface to TargetLowering::ExpandOperationResult to 
   take and return entire NODES that need a result expanded, not just
   the value.  This allows us to handle things like READCYCLECOUNTER,
   which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
   ExpandOperationResult.  This makes the result simpler and fully 
   general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
   i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
   allowing them to work with LegalizeDAGTypes.

LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.

llvm-svn: 44300
 2007-11-24 07:07:01 +00:00
Dale Johannesen
5fd9e7a615 Add parameter to getDwarfRegNum to permit targets 
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056
 2007-11-13 19:13:01 +00:00
Bill Wendling
934fcd87e7 Unifacalize the CALLSEQ{START,END} stuff. 
llvm-svn: 44045
 2007-11-13 09:19:02 +00:00
Bill Wendling
cc75435ebf Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
 2007-11-13 00:44:25 +00:00
Owen Anderson
aba398a5ce Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
 2007-11-12 07:39:39 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
 2007-11-11 19:50:10 +00:00
Evan Cheng
7d8deec92f Much improved pic jumptable codegen: 
Then:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        imull   $4, %ecx, %ecx
        leal    LJTI1_0-"L1$pb"(%eax), %edx
        addl    LJTI1_0-"L1$pb"(%ecx,%eax), %edx
        jmpl    *%edx

        .align  2
        .set L1_0_set_3,LBB1_3-LJTI1_0
        .set L1_0_set_2,LBB1_2-LJTI1_0
        .set L1_0_set_5,LBB1_5-LJTI1_0
        .set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

Now:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        addl    LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
        jmpl    *%eax

		.align  2
		.set L1_0_set_3,LBB1_3-"L1$pb"
		.set L1_0_set_2,LBB1_2-"L1$pb"
		.set L1_0_set_5,LBB1_5-"L1$pb"
		.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

llvm-svn: 43924
 2007-11-09 01:32:10 +00:00
Lauro Ramos Venancio
d8f2190c19 [ARM] Implement __builtin_thread_pointer. 
llvm-svn: 43892
 2007-11-08 17:20:05 +00:00
Rafael Espindola
ec025c3042 Move the LowerMEMCPY and LowerMEMCPYCall to a common place. 
Thanks for the suggestions Bill :-)

llvm-svn: 43742
 2007-11-05 23:12:20 +00:00
Lauro Ramos Venancio
f5081ba980 [ARM] Fix code generation for: 
static __thread struct {
    int a;
    int b;
} teste = {0, 0};

llvm-svn: 43722
 2007-11-05 18:33:37 +00:00
Duncan Sands
d1bdbd010b Eliminate the remaining uses of getTypeSize. This 
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688
 2007-11-05 00:04:43 +00:00
Rafael Espindola
27a8907a7c Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold 
and by restructuring the X86 version.

New I just have to move this to a common place :-)

llvm-svn: 43554
 2007-10-31 14:39:58 +00:00
Rafael Espindola
fae98471a9 Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
 2007-10-31 11:52:06 +00:00
Dale Johannesen
0774a9c549 Support non-POSIX hosts by removing use of strncasecmp. 
llvm-svn: 43364
 2007-10-25 21:54:43 +00:00
Evan Cheng
252d9ddb4d Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
llvm-svn: 43234
 2007-10-22 22:11:27 +00:00
Rafael Espindola
c751cbdb02 split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend. 
llvm-svn: 43176
 2007-10-19 14:35:17 +00:00
Chris Lattner
57e2fa4ba0 Add an easy microoptimization I noticed. 
llvm-svn: 43164
 2007-10-19 03:29:26 +00:00
Evan Cheng
0449186690 - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. 
- Fix some copy+paste bugs.

llvm-svn: 43153
 2007-10-18 22:40:57 +00:00
Evan Cheng
c852780685 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. 
llvm-svn: 43150
 2007-10-18 21:29:24 +00:00
Christopher Lamb
7f21e45b06 Fix a misnamed parameter. 
llvm-svn: 43145
 2007-10-18 19:29:45 +00:00
Chris Lattner
374b185092 legalizing the ret operation on f64 shouldn't introduce a new 
i64 bit convert needlessly.

llvm-svn: 43116
 2007-10-18 06:17:07 +00:00
Evan Cheng
33df6a6bed Revert 42908 for now. 
llvm-svn: 42960
 2007-10-14 05:57:21 +00:00
Dan Gohman
a75e4a62e6 Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908
 2007-10-12 14:53:36 +00:00
Dan Gohman
edc841fb53 Set ISD::FPOW to Expand. 
llvm-svn: 42881
 2007-10-11 23:21:31 +00:00
Dan Gohman
6df332f0cb Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to 
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
 2007-10-08 18:33:35 +00:00
Evan Cheng
f536e2f41e - Added a few target hooks to generate load / store instructions from / to any 
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621
 2007-10-05 01:32:41 +00:00
Dan Gohman
30ba45b569 Use empty() member functions when that's what's being tested for instead 
of comparing begin() and end().

llvm-svn: 42585
 2007-10-03 19:26:29 +00:00
Gordon Henriksen
9b5a117d01 AsmPrinters overriding getAnalysisUsage should call super. 
And not super's super, either.

llvm-svn: 42482
 2007-09-30 13:39:29 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!

llvm-svn: 42346
 2007-09-26 06:25:56 +00:00
Dan Gohman
99e8e1ff08 More explicit keywords. 
llvm-svn: 42316
 2007-09-25 20:27:06 +00:00
Evan Cheng
d675ed5400 Honor user-defined section specification of a global, ignores whether its initializer is null. 
llvm-svn: 42182
 2007-09-21 00:41:19 +00:00
Evan Cheng
267f595834 Enable if-conversion for ARM by default. 
llvm-svn: 42156
 2007-09-20 00:48:22 +00:00
Evan Cheng
9e2db47639 Avoid referencing deleted instruction. 
llvm-svn: 42153
 2007-09-19 21:48:07 +00:00
Dan Gohman
fb60c0dfed Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
 2007-09-14 20:33:02 +00:00
Bill Wendling
89ced2f9b1 Enable indirect encoding for the personality function 
llvm-svn: 41873
 2007-09-11 23:55:40 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Duncan Sands
c358890f73 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
 2007-09-11 14:10:23 +00:00
Evan Cheng
24e8e4d6ef 80 col. 
llvm-svn: 41812
 2007-09-10 22:22:23 +00:00
Chris Lattner
d4602cc0e7 Add some notes about better flag handling. 
llvm-svn: 41808
 2007-09-10 21:43:18 +00:00
Owen Anderson
4b71e55287 Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!

llvm-svn: 41758
 2007-09-07 04:06:50 +00:00
Dale Johannesen
81d6ecb886 Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632
 2007-08-31 04:03:46 +00:00