1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 12:43:36 +01:00
Commit Graph

211313 Commits

Author SHA1 Message Date
Simon Pilgrim
1d8b1112ab Fix MSVC natvis visualisation of llvm::FixedVectorTyID and ScalableVectorTyID
VectorTyID was replaced with FixedVectorTyID and ScalableVectorTyID
2021-02-15 13:43:31 +00:00
Caroline Concatto
9ea32f75fa [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse
This patch adds  a new intrinsic experimental.vector.reduce that takes a single
vector and returns a vector of matching type but with the original lane order
 reversed. For example:

```
vector.reverse(<A,B,C,D>) ==> <D,C,B,A>
```

The new intrinsic supports fixed and scalable vectors types.
The fixed-width vector relies on shufflevector to maintain existing behaviour.
Scalable vector uses the new ISD node - VECTOR_REVERSE.

This new intrinsic is one of the named shufflevector intrinsics proposed on the
mailing-list in the RFC at [1].

Patch by Paul Walker (@paulwalker-arm).

[1] https://lists.llvm.org/pipermail/llvm-dev/2020-November/146864.html

Differential Revision: https://reviews.llvm.org/D94883
2021-02-15 13:39:43 +00:00
David Green
b6252362a0 [ARM] Extend search for increment in load/store optimizer
Currently the findIncDecAfter will only look at the next instruction for
post-inc candidates in the load/store optimizer. This extends that to a
search through the current BB, until an instruction that modifies or
uses the increment reg is found. This allows more post-inc load/stores
and ldm/stm's to be created, especially in cases where a schedule might
move instructions further apart.

We make sure not to look any further for an SP, as that might invalidate
stack slots that are still in use.

Differential Revision: https://reviews.llvm.org/D95881
2021-02-15 13:17:21 +00:00
Simon Pilgrim
b1fe8fc506 [X86][AVX] Regenerate PSUBUS tests for slow/fast shuffle AVX2 targets
update_llc_test_checks.py isn't reporting when we don't have a usable prefix for a particular run any more - so we lost all AVX2 testing!
2021-02-15 12:00:29 +00:00
Simon Pilgrim
48bb3e0de6 [X86][SSE] Add missing USUBSAT test coverage
Before we start removing combineSubToSubus (PR40111) - make sure we have actually have test coverage for SUB(X,TRUNC(UMIN(ZEXT(X),Y))) -> USUBSAT(X,TRUNC(UMIN(Y,C)))) patterns
2021-02-15 11:38:23 +00:00
Sjoerd Meijer
e48baaecdb Recommit "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode"
This reverts commit effc3b079927a6dd3084b4ff712ec07f926366f0, with the build
problem fixed.
2021-02-15 11:33:00 +00:00
Max Kazantsev
262e4a75c1 [LoopLoadElim] Pass ScalarEvolution in old pass manager. PR49141
Loop canonicalization may end up deleting blocks from CFG. And
Scalar Evolution may still keep cached referenced to those blocks
unless updated properly.
2021-02-15 18:08:23 +07:00
Sjoerd Meijer
dda4f352fa Revert "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode"
This reverts commit cd6de0e8de4a5fd558580be4b1a07116914fc8ed.
2021-02-15 11:01:23 +00:00
Sjoerd Meijer
c1c4d25c71 [TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode
This refactors shouldFavorPostInc() and shouldFavorBackedgeIndex() into
getPreferredAddressingMode() so that we have one interface to steer LSR in
generating the preferred addressing mode.

Differential Revision: https://reviews.llvm.org/D96600
2021-02-15 10:44:15 +00:00
Fraser Cormack
adeeb489c1 [RISCV] Convert VSLIDE(UP|DOWN) nodes to "VL" versions (NFC)
This patch prepares the RISCV VSLIDEUP and VSLIDEDOWN custom nodes to
ones carrying additional mask and vector-length operands. This is
primarily so they can be used by both systems.

This also takes the opportunity to create some helper functions to deal
with the common task of getting the default (unmasked) VL operands.

Reviewed By: craig.topper, arcbbb

Differential Revision: https://reviews.llvm.org/D96505
2021-02-15 10:32:56 +00:00
Marco Antognini
78407e3dd3 Restore diagnostic handler after CodeGenAction::ExecuteAction
Fix dangling pointer to local variable and address some typos.

Reviewed By: xur

Differential Revision: https://reviews.llvm.org/D96487
2021-02-15 10:33:00 +00:00
Florian Hahn
40e47d0fef Recommit "[LTO] Use lto::backend for code generation."
This version of the patch includes a fix for the cfi failures.

(undoes the revert commit 7db390cc7738a9ba0ed7d4ca59ab6ea2e69c47e9)

It also undoes reverts of follow-up patches that also needed reverting
originally:

  * [LTO] Add option enable NewPM with LTOCodeGenerator.
    (undoes revert commit 0a17664b47c153aa26a0d31b4835f26375440ec6)

  * [LTOCodeGenerator] Use lto::Config for options (NFC)."
    (undoes revert commit b0a8e41cfff717ff067bf63412d6edb0280608cd)
2021-02-15 10:05:42 +00:00
LLVM GN Syncbot
803e1c570b [gn build] Port 5786f64a4ec8 2021-02-15 09:52:10 +00:00
Arlo Siemsen
d4eefe6819 Add ehcont section support
In the future Windows will enable Control-flow Enforcement Technology (CET aka shadow stacks). To protect the path where the context is updated during exception handling, the binary is required to enumerate valid unwind entrypoints in a dedicated section which is validated when the context is being set during exception handling.

This change allows llvm to generate the section that contains the appropriate symbol references in the form expected by the msvc linker.

This feature is enabled through a new module flag, ehcontguard, which was modelled on the cfguard flag.

The change includes a test that when the module flag is enabled the section is correctly generated.

The set of exception continuation information includes returns from exceptional control flow (catchret in llvm).

In order to collect catchret we:
1) Includes an additional flag on machine basic blocks to indicate that the given block is the target of a catchret operation,
2) Introduces a new machine function pass to insert and collect symbols at the start of each block, and
3) Combines these targets with the other EHCont targets that were already being collected.

Change originally authored by Daniel Frampton <dframpto@microsoft.com>

For more details, see MSVC documentation for `/guard:ehcont`
  https://docs.microsoft.com/en-us/cpp/build/reference/guard-enable-eh-continuation-metadata

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D94835
2021-02-15 14:27:12 +08:00
Craig Topper
14651b74aa [RISCV] Add i16 bswap and i8/i16 bitreverse tests to the Zbp tests. NFC
Maybe we should use GREVI directly for these rather than
promoting and then shifting right.
2021-02-14 18:44:26 -08:00
Carl Ritson
730fd62aad [AMDGPU] Add llvm.amdgcn.wqm.demote intrinsic
Add intrinsic which demotes all active lanes to helper lanes.
This is used to implement demote to helper Vulkan extension.

In practice demoting a lane to helper simply means removing it
from the mask of live lanes used for WQM/WWM/Exact mode.
Where the shader does not use WQM, demotes just become kills.

Additionally add llvm.amdgcn.live.mask intrinsic to complement
demote operations. In theory llvm.amdgcn.ps.live can be used
to detect helper lanes; however, ps.live can be moved by LICM.
The movement of ps.live cannot be remedied without changing
its type signature and such a change would require ps.live
users to update as well.

Reviewed By: piotr

Differential Revision: https://reviews.llvm.org/D94747
2021-02-15 08:45:46 +09:00
Cassie Jones
615b38354f [GlobalISel] Disable vector types in narrowScalarAddSub
The implementation for vectors is broken and doesn't seem to be used by
anything. Explicitly remove support for them, they can be added again
later when they're properly implemented.

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D95699
2021-02-14 18:06:32 -05:00
Cassie Jones
e7dde42613 [GlobalISel] Extract a narrowScalarAddSub method. NFC
Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D95426
2021-02-14 18:06:32 -05:00
LLVM GN Syncbot
615e1b5852 [gn build] Port 656ead1fb7db 2021-02-14 19:23:24 +00:00
cynecx
b676b43803 [llvm/Support] Add SHA256 implementation
Adds an *unaudited* SHA-256 implementation to `llvm/Support`. The ongoing lld-macho effort needs this to emit an adhoc code signature for macho files on macOS Big Sur.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D96540
2021-02-14 19:01:01 +00:00
David Green
348450bfbf [ARM] Move PhaseOrdering test to the correct place. NFC 2021-02-14 18:43:39 +00:00
Florian Hahn
a334ec01fc [ConstraintElimination] Fix variables used for pattern matching.
Re-using the matched variable in the pattern does not work as expected.
This patch fixes that by introducing a new variable for the 2nd level
match.
2021-02-14 18:42:37 +00:00
Nikita Popov
4566585f18 [BasicAA] Merge aliasGEP code paths
At this point, we can treat the case of GEP/GEP aliasing and
GEP/non-GEP aliasing in essentially the same way. The only
differences are that we need to do an additional negative GEP base
check, and that we perform a bailout on unknown sizes for the
GEP/non-GEP case (the latter exists only to limit compile-time).

This change is not quite NFC due to the peculiar effect that
the DecomposedGEP for V2 can actually be non-trivial even if V2
is not a GEP. The reason for this is that getUnderlyingObject()
can look through LCSSA phi nodes, while stripPointerCasts() doesn't.
This can lead to slightly better results if single-entry phi nodes
occur inside a loop, where looking through the phi node via aliasPhi()
would subject it to phi cycle equivalence restrictions. It would
probably make sense to adjust pointer cast stripping (for AA) to
handle this case, and ensure consistent results.
2021-02-14 19:35:36 +01:00
Nikita Popov
880c8747c1 [BasicAA] Add test for single arg phi in loop (NFC) 2021-02-14 19:35:36 +01:00
David Green
cf4298a67a [ARM] A couple of small MVE reduction tests from intrinsics. NFC
Also added a PhaseOrdering test, to make sure they are not broken by
VectorCombine cost changes.
2021-02-14 18:26:22 +00:00
Tony Tye
69551096db [AMDGPU] Limit memory scope for scratch, LDS and GDS
Changes for AMD GPU SIMemoryLegalizer:

- Limit the memory scope to maximum supported by the scratch, LDS and
  GDS address spaces.

- Improve assertion checking.

- Correct toSIAtomicScope argument name.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D96643
2021-02-14 17:34:12 +00:00
Kazu Hirata
9458e140a1 [AMDGPU] Fix build breakage 2021-02-14 09:02:55 -08:00
David Green
a801f8b66e [ARM] Add some tests for MVE lane interleaving. NFC 2021-02-14 16:51:18 +00:00
Kazu Hirata
ff49587cde [llvm] Use llvm::is_contained (NFC) 2021-02-14 08:36:20 -08:00
Kazu Hirata
955b5e24b3 [llvm] Fix header guards (NFC)
Identified with llvm-header-guard.
2021-02-14 08:36:18 -08:00
Kazu Hirata
58892aceb7 [Analysis] Use ListSeparator (NFC) 2021-02-14 08:36:14 -08:00
Nikita Popov
304d2b10bb [BasicAA] Avoid duplicate query for GEPs with identical offsets (NFCI)
For two GEPs with identical offsets, we currently first perform
a base address query without size information, and then if it is
MayAlias, perform another with size information. This is pointless,
as the latter query should produce strictly better results.

This was not quite true historically due to the way that NoAlias
assumptions were handled, but that issue has since been resolved.
2021-02-14 17:18:28 +01:00
Nikita Popov
8bf924114e [BasicAA] Use index difference to detect GEPs with identical indexes
We currently detect GEPs that have exactly the same indexes by
comparing the Offsets and VarIndices. However, the latter implicitly
performs equality comparisons between two values, which is not
generally legal inside BasicAA, due to the possibility of comparisons
across phi cycles.

I believe that in this particular instance this actually ends up being
unproblematic, at least I wasn't able to come up with any cases that
could result in an incorrect root query result.

In the interest of being defensive, compute GetIndexDifference earlier
(which knows how to handle phi cycles properly) and use the result of
that to determine whether the offsets are identical.
2021-02-14 17:11:03 +01:00
aqjune
4a7f071301 [ValueTracking] Dereferenced pointers are noundef
This is a follow-up of D95238's LangRef update.
This patch updates `programUndefinedIfUndefOrPoison(V)` to return true if
`V` is used by any memory-accessing instruction.
Interestingly, this affected many tests in Attributors, mainly about adding noundefs.
The tests are updated using llvm/utils/update_test_checks.py. I checked that the diffs
are about updating noundefs.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D96642
2021-02-14 22:50:48 +09:00
Sanjay Patel
58d04ec009 [InstCombine] fold fdiv with pow divisor (PR49147)
This is unusual in the general (non-reciprocal) case because we need
an extra instruction, but that should be better for general FP
reassociation and codegen. We conservatively check for "arcp" FMF
here as we do with existing fdiv folds, but it is not strictly
necessary to have that.

This is part of solving:
https://llvm.org/PR49147
(The powi variant potentially has a different constraint.)

Differential Revision: https://reviews.llvm.org/D96648
2021-02-14 08:07:36 -05:00
Juneyoung Lee
2ab0e3b676 [InstCombine] Add nonnull(select c, null, p) tests (NFC) 2021-02-14 22:03:41 +09:00
Juneyoung Lee
9861dbbf5f [LoopVectorize] Fix VPRecipeBuilder::createEdgeMask to correctly generate the mask
This patch fixes pr48832 by correctly generating the mask when a poison value is involved.

Consider this CFG (which is a part of the input):

```
for.body:                                         ; preds = %for.cond
  br i1 true, label %cond.false, label %land.rhs

land.rhs:                                         ; preds = %for.body
  br i1 poison, label %cond.end, label %cond.false

cond.false:                                       ; preds = %for.body, %land.rhs
  br label %cond.end

cond.end:                                         ; preds = %land.rhs, %cond.false
  %cond = phi i32 [ 0, %cond.false ], [ 1, %land.rhs ]

```

The path for.body -> land.rhs -> cond.end should be taken when 'select i1 false, i1 poison, i1 false' holds (which means it's never taken); but VPRecipeBuilder::createEdgeMask was emitting 'and i1 false, poison' instead.
The former one successfully blocks poison propagation whereas the latter one doesn't, making the condition poison and thus causing the miscompilation.

SimplifyCFG has a similar bug (which didn't expose a real-world bug yet), and a patch for this is also ongoing (see https://reviews.llvm.org/D95026).

Reviewed By: bjope

Differential Revision: https://reviews.llvm.org/D95217
2021-02-14 21:12:34 +09:00
Kazu Hirata
e5eb765288 [CodeGen] Use range-based for loops (NFC) 2021-02-13 20:41:39 -08:00
Kazu Hirata
48654a06bf [Analysis] Drop unnecessary const from return types (NFC)
Identified with readability-const-return-type.
2021-02-13 20:41:38 -08:00
Kazu Hirata
d66c382a33 [TableGen] Use ListSeparator (NFC) 2021-02-13 20:41:36 -08:00
Ben Shi
fd0f322cf0 [AVR] Fix a bug in 16-bit shifts
Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D96590
2021-02-14 11:54:55 +08:00
Teresa Johnson
0e8ee7dcc3 [gold] Add case being tested by equivalent lld test
The new tests added by 1487747e990ce9f8851f3d92c3006a74134d7518 for lld
and gold plugin were largely equivalent, but the gold one was missing
one of the cases added to lld. Add that test to the gold plugin version.
2021-02-13 17:09:56 -08:00
Teresa Johnson
f4839c7303 [LTT] Address post-review comments (NFC)
Implement some post-review cleanup suggestions for D96083.
2021-02-13 15:52:59 -08:00
Fangrui Song
8b3392c500 ELFObjectWriter: Simplify
* Delete unused ELFSymbolData::operator<
* Inline createStringTable
* Fix a comment
* Change align to return uint64_t
2021-02-13 14:52:30 -08:00
Craig Topper
9d5ee57922 [RISCV] Rename the RVVBaseAddr ComplexPattern to just BaseAddr and use it to merge some scalar load/store patterns too. 2021-02-13 12:01:51 -08:00
Fangrui Song
07bc1859f5 ELFObjectWriter: Delete redundant registerSymbol
MCELFStreamer::changeSection has registered the group signature symbol.
2021-02-13 12:01:37 -08:00
Fangrui Song
d33006d182 ELFObjectWriter: Don't sort non-local symbols
As we don't sort local symbols, don't sort non-local symbols.  This makes
non-local symbols appear in their register order, which matches GNU as. The
register order is nice in that you can write tests with interleaved CHECK
prefixes, e.g.

```
// CHECK: something about foo
.globl foo
foo:
// CHECK: something about bar
.globl bar
bar:
```

With the lexicographical order, the user needs to place lexicographical smallest
symbol first or keep CHECK prefixes in one place.
2021-02-13 10:32:27 -08:00
Sanjay Patel
17f939474e [InstCombine] add tests for pow() divisor; NFC 2021-02-13 13:04:38 -05:00
Nikita Popov
4d31ccb85f [IRBuilder] Remove Align-related deprecated APIs
This removes IRBuilder methods accepting unsigned alignments
in favor of their Align/MaybeAlign variants. These methods have
been deprecated for more than a year at this point, so they
should be safe to remove.
2021-02-13 16:42:37 +01:00
David Green
0472de536c [ARM] Fix duplicate fdiv tests, changing them to frem. NFC 2021-02-13 15:16:11 +00:00