1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
Commit Graph

944 Commits

Author SHA1 Message Date
Evan Cheng
99a186e39f Clean up.
llvm-svn: 56300
2008-09-18 07:27:23 +00:00
Evan Cheng
b44e839f76 Cosmetic.
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
Evan Cheng
f2c04a10e6 Fix addrmode1 instruction encodings; fix bx_ret encoding.
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
Evan Cheng
d268288d39 Specify instruction encoding using range list to avoid endianess issues.
llvm-svn: 56276
2008-09-17 07:16:21 +00:00
Bill Wendling
932818c75a Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.

llvm-svn: 56251
2008-09-16 21:48:12 +00:00
Bill Wendling
1a240c8033 - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
2008-09-16 21:12:30 +00:00
Dan Gohman
fa32c7c6d9 Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Evan Cheng
63b98ccd5e Fix random abort.
llvm-svn: 56184
2008-09-13 01:55:59 +00:00
Dan Gohman
3450a8252f Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183
2008-09-13 01:54:27 +00:00
Evan Cheng
775a37e4b4 Typo.
llvm-svn: 56182
2008-09-13 01:44:01 +00:00
Evan Cheng
200cdea934 Rely on instruction format to determine so_reg operand for now.
llvm-svn: 56181
2008-09-13 01:38:29 +00:00
Evan Cheng
0a3a595612 Revert 56176. All those instruction formats are still needed.
llvm-svn: 56180
2008-09-13 01:35:33 +00:00
Evan Cheng
1ac0a5f278 Accidentially flipped the condition.
llvm-svn: 56179
2008-09-13 01:29:57 +00:00
Evan Cheng
d68f2947a9 Add debug dumps.
llvm-svn: 56178
2008-09-13 01:15:21 +00:00
Evan Cheng
18fd8337b3 Eliminate unnecessary instruction formats.
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
Evan Cheng
66e7651a16 Addrmode 1 S bit can be dynamically set. Look for CPSR def.
llvm-svn: 56172
2008-09-12 22:45:55 +00:00
Evan Cheng
adf6720626 Rewrite address mode 1 code emission routines.
llvm-svn: 56171
2008-09-12 22:01:15 +00:00
Dan Gohman
89660301e3 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Jim Grosbach
a25a322741 udpate header comment: s/VP/VFP/
llvm-svn: 56126
2008-09-11 21:41:29 +00:00
Dale Johannesen
1ed08a58d1 Fix logic for not emitting no-dead-strip for some
objects in llvm.used (thanks Anton).  Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).

llvm-svn: 55973
2008-09-09 01:21:22 +00:00
Dan Gohman
fedd10cd95 Delete an unused variable.
llvm-svn: 55915
2008-09-08 16:28:17 +00:00
Dan Gohman
e1f9be27bc Tidy up several unbeseeming casts from pointer to intptr_t.
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
Dale Johannesen
9e4d101fab Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).

llvm-svn: 55753
2008-09-04 00:47:13 +00:00
Evan Cheng
126bd60288 Add Mac OS X compatible JIT callback routine.
llvm-svn: 55625
2008-09-02 07:49:03 +00:00
Evan Cheng
e97c48a34a Revamp ARM JIT.
llvm-svn: 55624
2008-09-02 06:52:38 +00:00
Evan Cheng
738426a2a1 Control flow instruction encodings.
llvm-svn: 55601
2008-09-01 08:25:56 +00:00
Evan Cheng
36170e63a3 ldm / stm instruction encodings.
llvm-svn: 55599
2008-09-01 07:48:18 +00:00
Evan Cheng
01019d7909 AXI2 and AXI3 instruction encodings.
llvm-svn: 55598
2008-09-01 07:34:13 +00:00
Evan Cheng
fdae49e627 Reorganize instruction formats again; AXI1 encoding.
llvm-svn: 55597
2008-09-01 07:19:00 +00:00
Evan Cheng
26305b192f addrmode3 instruction encodings.
llvm-svn: 55596
2008-09-01 07:00:14 +00:00
Evan Cheng
eb40cb3e42 Reorganize some instruction format definitions. No functionality change.
llvm-svn: 55594
2008-09-01 01:51:14 +00:00
Evan Cheng
fa095aec1e Rest of addrmode2 instruction encodings.
llvm-svn: 55593
2008-09-01 01:27:33 +00:00
Evan Cheng
4c8338c0d3 Addr2 word / byte load encodings.
llvm-svn: 55591
2008-08-31 19:02:21 +00:00
Evan Cheng
94f3d276c6 Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
llvm-svn: 55590
2008-08-31 18:32:16 +00:00
Evan Cheng
3fb02ae0b6 TableGen'ing instruction encodings.
llvm-svn: 55533
2008-08-29 07:42:03 +00:00
Evan Cheng
b38decd917 addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
llvm-svn: 55531
2008-08-29 07:40:52 +00:00
Evan Cheng
5150e3da45 MVN is addrmode1.
llvm-svn: 55530
2008-08-29 07:36:24 +00:00
Evan Cheng
f90bc9a050 More refactoring.
llvm-svn: 55528
2008-08-29 06:41:12 +00:00
Evan Cheng
c50df85672 Refactor ARM instruction format definitions into a separate file. No functionality changes.
llvm-svn: 55518
2008-08-28 23:39:26 +00:00
Gabor Greif
86c795a8ca erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
Gabor Greif
4b86114f92 disallow direct access to SDValue::ResNo, provide a getter instead
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
Owen Anderson
5fef19facf Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375
2008-08-26 18:03:31 +00:00
Chris Lattner
fe3155fc62 Switch the asmprinter (.ll) and all the stuff it requires over to
use raw_ostream instead of std::ostream.  Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).

Other interesting changes:
 1) This makes Value::print be non-virtual.
 2) AP[S]Int and ConstantRange can no longer print to ostream directly, 
    use raw_ostream instead.
 3) This fixes a bug in raw_os_ostream where it didn't flush itself 
    when destroyed.
 4) This adds a new SDNode::print method, instead of only allowing "dump".


A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream 
versions.

This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.

llvm-svn: 55263
2008-08-23 22:23:09 +00:00
Dan Gohman
a9d5f9b006 Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219
2008-08-23 02:25:05 +00:00
Dan Gohman
4b801d38a1 Simplify SelectRoot's interface, and factor out some common code
from all targets.

llvm-svn: 55124
2008-08-21 16:36:34 +00:00
Owen Anderson
2c1d54952b Use raw_ostream throughout the AsmPrinter.
llvm-svn: 55092
2008-08-21 00:14:44 +00:00
Evan Cheng
3b0cb367c0 ARM asm printer can't handle dwarf info yet.
llvm-svn: 54913
2008-08-18 08:52:48 +00:00
Anton Korobeynikov
4b6a6e3e8d Move ARM to pluggable asmprinter
llvm-svn: 54889
2008-08-17 13:55:10 +00:00
Owen Anderson
600a8ca0d5 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
llvm-svn: 54802
2008-08-14 22:49:33 +00:00
Jim Grosbach
df52e6897d Whitespace cleanup. Test commit.
llvm-svn: 54695
2008-08-12 18:34:45 +00:00
Anton Korobeynikov
8d77445753 Handle visibility printing with all generality. Remove bunch of duplicate code.
llvm-svn: 54540
2008-08-08 18:25:07 +00:00
Evan Cheng
804e157031 Undo most of r54519.
llvm-svn: 54534
2008-08-08 17:56:50 +00:00
Evan Cheng
4708df4776 It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
llvm-svn: 54519
2008-08-08 06:56:16 +00:00
Anton Korobeynikov
0c8d06f030 Switch ARM to new section handling stuff
llvm-svn: 54458
2008-08-07 09:54:23 +00:00
Dan Gohman
9742f7772d Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Evan Cheng
d4eb684258 Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
llvm-svn: 54004
2008-07-25 00:55:17 +00:00
Dan Gohman
8981962672 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728
2008-07-17 19:10:17 +00:00
Chris Lattner
4f20448c91 add support for returning i128, PR2532.
llvm-svn: 53472
2008-07-11 20:53:00 +00:00
Dan Gohman
d7a32ecde2 Trim unnecessary #includes.
llvm-svn: 53471
2008-07-11 20:38:31 +00:00
Dale Johannesen
11d39779a1 Emit debug info for data-only files. ARM version.
llvm-svn: 53360
2008-07-09 21:20:54 +00:00
Evan Cheng
f51c436a1b Back out 53254. It broke ppc debug info codegen.
llvm-svn: 53280
2008-07-09 06:36:53 +00:00
Dale Johannesen
d609d7166c Make debug info come out in data-only files.
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason.  I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.

llvm-svn: 53254
2008-07-08 21:56:22 +00:00
Dan Gohman
cd25487258 Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212
2008-07-07 23:14:23 +00:00
Dan Gohman
7fb6670108 Minor const-correctness fixes.
llvm-svn: 53196
2008-07-07 20:06:06 +00:00
Dan Gohman
955fdc7a4c Add explicit keywords.
llvm-svn: 53179
2008-07-07 18:00:37 +00:00
Duncan Sands
3ea6f15708 Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes.  No change if the
new LegalizeTypes infrastructure is not turned on.

llvm-svn: 53137
2008-07-04 11:47:58 +00:00
Evan Cheng
1f6148a84c - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.

llvm-svn: 53097
2008-07-03 09:09:37 +00:00
Owen Anderson
604f9f722d Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.

llvm-svn: 53058
2008-07-02 23:41:07 +00:00
Duncan Sands
21e2a711e3 Add a new getMergeValues method that does not need
to be passed the list of value types, and use this
where appropriate.  Inappropriate places are where
the value type list is already known and may be
long, in which case the existing method is more
efficient.

llvm-svn: 53035
2008-07-02 17:40:58 +00:00
Dan Gohman
c8097f8c8c Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943
2008-07-01 00:05:16 +00:00
Dan Gohman
6cc648891b Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.

This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.

This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.

llvm-svn: 52924
2008-06-30 20:59:49 +00:00
Evan Cheng
3f664b6fd3 Split scheduling from instruction selection.
llvm-svn: 52923
2008-06-30 20:45:06 +00:00
Duncan Sands
c882a4eba9 Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT.  On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable.  So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).

llvm-svn: 52893
2008-06-30 10:19:09 +00:00
Duncan Sands
d634afe3aa Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044
2008-06-06 12:08:01 +00:00
Dale Johannesen
c0cd6cd4d4 Add StringConstantPrefix to control what the
assembler names of string constants look like.

llvm-svn: 51909
2008-06-03 18:09:06 +00:00
Dale Johannesen
e6977495aa Handle quoted names when constructing $stub's,
$non_lazy_ptr's and $lazy_ptr's.

llvm-svn: 51277
2008-05-19 21:38:18 +00:00
Dan Gohman
f9d5689496 Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091
2008-05-14 01:58:56 +00:00
Dan Gohman
bab18cae46 Clean up the use of static and anonymous namespaces. This turned up
several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017
2008-05-13 00:00:25 +00:00
Chris Lattner
d46c148cf8 Match things like 'armv5tejl-unknown-linux-gnu' for PR2290
llvm-svn: 50698
2008-05-06 02:29:28 +00:00
Dan Gohman
0285c1e9bb Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.

llvm-svn: 50359
2008-04-28 17:15:20 +00:00
Nicolas Geoffray
1f3211af01 Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
the stub will resolve.

llvm-svn: 49814
2008-04-16 20:46:05 +00:00
Nicolas Geoffray
82baa2d2c6 Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Dan Gohman
8d46278998 Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.

llvm-svn: 49666
2008-04-14 17:55:48 +00:00
Dan Gohman
15edbf989f Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.

llvm-svn: 49572
2008-04-12 04:36:06 +00:00
Evan Cheng
a38ae9c502 Unbreak ARM / Thumb soft FP support.
llvm-svn: 49012
2008-04-01 01:50:16 +00:00
Evan Cheng
38a755499d Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
Chris Lattner
49e9edd6f6 Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.

llvm-svn: 48963
2008-03-30 18:22:13 +00:00
Dan Gohman
2b96ce84aa Add explicit keywords.
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
Dan Gohman
22002efa15 A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.

llvm-svn: 48800
2008-03-25 21:45:14 +00:00
Evan Cheng
3da2a15397 Add \t after .set. Fix by Jay Freeman.
llvm-svn: 48753
2008-03-24 23:36:49 +00:00
Duncan Sands
4153fc30c9 Introduce a new node for holding call argument
flags.  This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines.  There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness.  As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.

llvm-svn: 48640
2008-03-21 09:14:45 +00:00
Evan Cheng
11d2c09adc Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Dan Gohman
8e3c88c4e9 Use PassManagerBase instead of FunctionPassManager for functions
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256
2008-03-11 22:29:46 +00:00
Evan Cheng
7d9e5a7680 Default ISD::PREFETCH to expand.
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
Dale Johannesen
e6b0009792 Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff.  Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and 
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)

llvm-svn: 48122
2008-03-10 02:17:22 +00:00
Evan Cheng
dba1dfe962 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
Evan Cheng
18064ddb5b Refactor code. Remove duplicated functions that basically do the same thing as
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.

llvm-svn: 47927
2008-03-05 00:59:57 +00:00
Evan Cheng
f8b1257d2e Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
Bill Wendling
2cae66e28b Final de-tabification.
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
Evan Cheng
7553230e3a Spiller now remove unused spill slots.
llvm-svn: 47657
2008-02-27 03:04:06 +00:00
Bill Wendling
50f5c4be14 Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!

llvm-svn: 47625
2008-02-26 21:11:01 +00:00
Anton Korobeynikov
4f6e612973 Remove bunch of gcc 4.3-related warnings from Target
llvm-svn: 47369
2008-02-20 11:22:39 +00:00
Andrew Lenharth
da54523742 I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
llvm-svn: 47213
2008-02-16 14:46:26 +00:00
Chris Lattner
d55c26a77d Handle \n's in value names for more targets. The asm printers
really really really need refactoring :(

llvm-svn: 47171
2008-02-15 19:04:54 +00:00
Duncan Sands
0056f1e823 In TargetLowering::LowerCallTo, don't assert that
the return value is zero-extended if it isn't
sign-extended.  It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned".  Currently
isSExt is set when signed, and nothing is
set otherwise.  This should be right for all
calls to standard library routines.

llvm-svn: 47122
2008-02-14 17:28:50 +00:00
Nate Begeman
1ef1013b6c Change how FP immediates are handled.
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
   if it is legal.

This allows ConstantFP to be handled like Constant, allowing for 
targets that can encode FP immediates as MachineOperands.

As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants!  Hooray.

llvm-svn: 47121
2008-02-14 08:57:00 +00:00
Dan Gohman
99b38405e3 Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference. 

llvm-svn: 47096
2008-02-13 22:28:48 +00:00
Chris Lattner
57f2088225 don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
DAGCombine is now quite good at zapifying them.

llvm-svn: 47053
2008-02-13 07:35:30 +00:00
Dan Gohman
09023887f8 Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.

llvm-svn: 47039
2008-02-13 00:35:47 +00:00
Dale Johannesen
4621e574c9 __DATA not __DATA__ is the right segment name on darwin.
Spotted by Nick Kledzik.

llvm-svn: 47037
2008-02-12 23:35:09 +00:00
Nate Begeman
589ecad41d Remove some dead code
llvm-svn: 47036
2008-02-12 22:54:40 +00:00
Dan Gohman
cabaec582f Rename MRegisterInfo to TargetRegisterInfo.
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Evan Cheng
90f03a0b88 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Dan Gohman
f00842e086 Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.

llvm-svn: 46827
2008-02-06 22:27:42 +00:00
Evan Cheng
1c67dcaae7 Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
llvm-svn: 46724
2008-02-04 23:06:48 +00:00
Nate Begeman
2b00217d58 This method should be virtual
llvm-svn: 46723
2008-02-04 23:04:24 +00:00
Nate Begeman
8285430ed7 Eliminate some redundant code.
llvm-svn: 46720
2008-02-04 21:44:06 +00:00
Chris Lattner
e926ece00b explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
llvm-svn: 46676
2008-02-03 05:43:57 +00:00
Chris Lattner
df36b95e00 don't do ReplaceUses on a result that doesn't exist.
llvm-svn: 46673
2008-02-03 03:20:59 +00:00
Evan Cheng
f61d1115af Get rid of the annoying blank lines before labels.
llvm-svn: 46667
2008-02-02 08:39:46 +00:00
Evan Cheng
c57ec111f2 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659
2008-02-02 04:07:54 +00:00
Evan Cheng
2a533e6894 Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
llvm-svn: 46623
2008-01-31 21:00:00 +00:00
Dan Gohman
4326d513ab Create a new class, MemOperand, for describing memory references
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.

Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.

Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.

llvm-svn: 46585
2008-01-31 00:25:39 +00:00
Evan Cheng
918b9c9335 Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.

llvm-svn: 46562
2008-01-30 18:18:23 +00:00
Dan Gohman
13d1327796 Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.

llvm-svn: 46538
2008-01-30 00:15:11 +00:00
Bill Wendling
5b6f587a80 If the function has no machine instructions, then emit a "nop" so that
the function label isn't associated with something it shouldn't be.

llvm-svn: 46449
2008-01-28 09:15:03 +00:00
Duncan Sands
aff4eef6df The last pieces needed for loading arbitrary
precision integers.  This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on.  While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.

llvm-svn: 46280
2008-01-23 20:39:46 +00:00
Dale Johannesen
a54401ee30 Honor explicit section information on Darwin.
llvm-svn: 46267
2008-01-23 00:58:14 +00:00
Dale Johannesen
0e1328e880 Revert the part of 45849 that treated weak globals
as weak globals rather than commons.  While not wrong,
this change tickled a latent bug in Darwin's strip,
so revert it for now as a workaround.

llvm-svn: 46147
2008-01-17 23:36:04 +00:00
Chris Lattner
41717f6989 This commit changes:
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner
6846e346a8 rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
2008-01-15 22:02:54 +00:00
Owen Anderson
946d55e773 Remove DefInst from LiveVariables::VarInfo. Use the facilities on MachineRegisterInfo instead.
llvm-svn: 46016
2008-01-15 22:02:46 +00:00
Chris Lattner
0293fca6d8 rename MachineInstr::setInstrDescriptor -> setDesc
llvm-svn: 45871
2008-01-11 18:10:50 +00:00
Dale Johannesen
83852e3451 Weak zeroes don't go in bss on Darwin.
llvm-svn: 45849
2008-01-11 01:59:45 +00:00
Chris Lattner
9b4f2b2316 get def use info more correct.
llvm-svn: 45821
2008-01-10 05:12:37 +00:00
Evan Cheng
9de4f35e9f Only mark instructions that load a single value without extension as isSimpleLoad = 1.
llvm-svn: 45727
2008-01-07 23:56:57 +00:00
Chris Lattner
f83aae613c rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner
57e851edfe Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.

llvm-svn: 45692
2008-01-07 06:42:05 +00:00
Chris Lattner
9d38dfa4a5 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
llvm-svn: 45680
2008-01-07 03:13:06 +00:00
Chris Lattner
55343065e3 remove MachineOpCode typedef.
llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Chris Lattner
f7f96d818f Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
2008-01-07 01:56:04 +00:00
Owen Anderson
f19692b2f6 Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...

llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Chris Lattner
14310afe42 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner
5489888580 rename isStore -> mayStore to more accurately reflect what it captures.
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
Chris Lattner
2bb919b542 remove explicit isStore flags that are now inferrable.
llvm-svn: 45653
2008-01-06 05:55:01 +00:00
Owen Anderson
2adf8c5533 Move some more functionality from MRegisterInfo to TargetInstrInfo.
llvm-svn: 45603
2008-01-04 23:57:37 +00:00
Owen Anderson
e6856128ab Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner
1285ec2ae7 Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson
ae7e2c1e03 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.

llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Chris Lattner
96167aa93c Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
2007-12-31 04:13:23 +00:00
Chris Lattner
9e5cc35593 Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464
2007-12-30 23:10:15 +00:00
Chris Lattner
12477d46b4 Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
Chris Lattner
fac8748ca7 use simplified operand addition methods.
llvm-svn: 45437
2007-12-30 01:01:54 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Chris Lattner
8193d4af33 remove attribution from lib Makefiles.
llvm-svn: 45415
2007-12-29 20:09:26 +00:00
Evan Cheng
64a1febf9a Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
Evan Cheng
fdd03d0589 Doh
llvm-svn: 44694
2007-12-08 01:01:07 +00:00
Evan Cheng
28c2b7e647 Fix a compilation warning.
llvm-svn: 44692
2007-12-08 01:00:31 +00:00
Evan Cheng
8464a0bf00 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.

llvm-svn: 44600
2007-12-05 03:14:33 +00:00
Evan Cheng
58b387dfb0 Remove redundant foldMemoryOperand variants and other code clean up.
llvm-svn: 44517
2007-12-02 08:30:39 +00:00
Evan Cheng
79e8b92dc3 Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
llvm-svn: 44479
2007-12-01 02:07:52 +00:00
Chris Lattner
706eb604ae several entries got significantly better, though they still aren't done.
llvm-svn: 44382
2007-11-27 22:41:52 +00:00
Chris Lattner
d2ee2dad04 implement a trivial readme entry.
llvm-svn: 44380
2007-11-27 22:36:16 +00:00
Chris Lattner
28262fbaf2 Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to 
   take and return entire NODES that need a result expanded, not just
   the value.  This allows us to handle things like READCYCLECOUNTER,
   which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
   ExpandOperationResult.  This makes the result simpler and fully 
   general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
   i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
   allowing them to work with LegalizeDAGTypes.

LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.

llvm-svn: 44300
2007-11-24 07:07:01 +00:00
Dale Johannesen
5fd9e7a615 Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056
2007-11-13 19:13:01 +00:00
Bill Wendling
934fcd87e7 Unifacalize the CALLSEQ{START,END} stuff.
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
Bill Wendling
cc75435ebf Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
2007-11-13 00:44:25 +00:00
Owen Anderson
aba398a5ce Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
2007-11-12 07:39:39 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
2007-11-11 19:50:10 +00:00
Evan Cheng
7d8deec92f Much improved pic jumptable codegen:
Then:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        imull   $4, %ecx, %ecx
        leal    LJTI1_0-"L1$pb"(%eax), %edx
        addl    LJTI1_0-"L1$pb"(%ecx,%eax), %edx
        jmpl    *%edx

        .align  2
        .set L1_0_set_3,LBB1_3-LJTI1_0
        .set L1_0_set_2,LBB1_2-LJTI1_0
        .set L1_0_set_5,LBB1_5-LJTI1_0
        .set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

Now:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        addl    LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
        jmpl    *%eax

		.align  2
		.set L1_0_set_3,LBB1_3-"L1$pb"
		.set L1_0_set_2,LBB1_2-"L1$pb"
		.set L1_0_set_5,LBB1_5-"L1$pb"
		.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

llvm-svn: 43924
2007-11-09 01:32:10 +00:00
Lauro Ramos Venancio
d8f2190c19 [ARM] Implement __builtin_thread_pointer.
llvm-svn: 43892
2007-11-08 17:20:05 +00:00
Rafael Espindola
ec025c3042 Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)

llvm-svn: 43742
2007-11-05 23:12:20 +00:00
Lauro Ramos Venancio
f5081ba980 [ARM] Fix code generation for:
static __thread struct {
    int a;
    int b;
} teste = {0, 0};

llvm-svn: 43722
2007-11-05 18:33:37 +00:00
Duncan Sands
d1bdbd010b Eliminate the remaining uses of getTypeSize. This
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688
2007-11-05 00:04:43 +00:00
Rafael Espindola
27a8907a7c Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
and by restructuring the X86 version.

New I just have to move this to a common place :-)

llvm-svn: 43554
2007-10-31 14:39:58 +00:00
Rafael Espindola
fae98471a9 Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
2007-10-31 11:52:06 +00:00
Dale Johannesen
0774a9c549 Support non-POSIX hosts by removing use of strncasecmp.
llvm-svn: 43364
2007-10-25 21:54:43 +00:00
Evan Cheng
252d9ddb4d Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
llvm-svn: 43234
2007-10-22 22:11:27 +00:00
Rafael Espindola
c751cbdb02 split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.
llvm-svn: 43176
2007-10-19 14:35:17 +00:00
Chris Lattner
57e2fa4ba0 Add an easy microoptimization I noticed.
llvm-svn: 43164
2007-10-19 03:29:26 +00:00
Evan Cheng
0449186690 - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.

llvm-svn: 43153
2007-10-18 22:40:57 +00:00
Evan Cheng
c852780685 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
llvm-svn: 43150
2007-10-18 21:29:24 +00:00
Christopher Lamb
7f21e45b06 Fix a misnamed parameter.
llvm-svn: 43145
2007-10-18 19:29:45 +00:00
Chris Lattner
374b185092 legalizing the ret operation on f64 shouldn't introduce a new
i64 bit convert needlessly.

llvm-svn: 43116
2007-10-18 06:17:07 +00:00
Evan Cheng
33df6a6bed Revert 42908 for now.
llvm-svn: 42960
2007-10-14 05:57:21 +00:00
Dan Gohman
a75e4a62e6 Change the names used for internal labels to use the current
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908
2007-10-12 14:53:36 +00:00
Dan Gohman
edc841fb53 Set ISD::FPOW to Expand.
llvm-svn: 42881
2007-10-11 23:21:31 +00:00
Dan Gohman
6df332f0cb Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
2007-10-08 18:33:35 +00:00
Evan Cheng
f536e2f41e - Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621
2007-10-05 01:32:41 +00:00
Dan Gohman
30ba45b569 Use empty() member functions when that's what's being tested for instead
of comparing begin() and end().

llvm-svn: 42585
2007-10-03 19:26:29 +00:00
Gordon Henriksen
9b5a117d01 AsmPrinters overriding getAnalysisUsage should call super.
And not super's super, either.

llvm-svn: 42482
2007-09-30 13:39:29 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!

llvm-svn: 42346
2007-09-26 06:25:56 +00:00
Dan Gohman
99e8e1ff08 More explicit keywords.
llvm-svn: 42316
2007-09-25 20:27:06 +00:00
Evan Cheng
d675ed5400 Honor user-defined section specification of a global, ignores whether its initializer is null.
llvm-svn: 42182
2007-09-21 00:41:19 +00:00
Evan Cheng
267f595834 Enable if-conversion for ARM by default.
llvm-svn: 42156
2007-09-20 00:48:22 +00:00
Evan Cheng
9e2db47639 Avoid referencing deleted instruction.
llvm-svn: 42153
2007-09-19 21:48:07 +00:00
Dan Gohman
fb60c0dfed Remove isReg, isImm, and isMBB, and change all their users to use
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
2007-09-14 20:33:02 +00:00
Bill Wendling
89ced2f9b1 Enable indirect encoding for the personality function
llvm-svn: 41873
2007-09-11 23:55:40 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Duncan Sands
c358890f73 Fold the adjust_trampoline intrinsic into
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
2007-09-11 14:10:23 +00:00
Evan Cheng
24e8e4d6ef 80 col.
llvm-svn: 41812
2007-09-10 22:22:23 +00:00
Chris Lattner
d4602cc0e7 Add some notes about better flag handling.
llvm-svn: 41808
2007-09-10 21:43:18 +00:00
Owen Anderson
4b71e55287 Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!

llvm-svn: 41758
2007-09-07 04:06:50 +00:00
Dale Johannesen
81d6ecb886 Enhance APFloat to retain bits of NaNs (fixes oggenc).
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632
2007-08-31 04:03:46 +00:00
Raul Herbster
ffa8296e3f Instruction formats added used to generate multiply instructions of V5TE.
llvm-svn: 41629
2007-08-30 23:34:14 +00:00
Raul Herbster
7f1a7dc4e2 Unused relocation type reloc_arm_absolute removed.
llvm-svn: 41628
2007-08-30 23:31:35 +00:00
Raul Herbster
db2f42989b Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly.
llvm-svn: 41627
2007-08-30 23:29:26 +00:00
Raul Herbster
49b44eae34 ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
llvm-svn: 41626
2007-08-30 23:25:47 +00:00
Raul Herbster
26e15aed5c JITInfo now resolves function addrs and also relocations. It always emits a stub.
llvm-svn: 41625
2007-08-30 23:21:27 +00:00
Evan Cheng
58ea935f6f Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
llvm-svn: 41597
2007-08-30 05:52:20 +00:00
Evan Cheng
8c896cc115 Initial JIT support for ARM by Raul Fernandes Herbster.
llvm-svn: 40887
2007-08-07 01:37:15 +00:00
Dan Gohman
352de5aeb9 More explicit keywords.
llvm-svn: 40757
2007-08-02 21:21:54 +00:00
Evan Cheng
ab0a826b88 Indexed loads each has 2 outputs.
llvm-svn: 40658
2007-08-01 00:12:08 +00:00
Dan Gohman
75473b49ea More explicit keywords.
llvm-svn: 40589
2007-07-30 14:51:59 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is
still under discussion.

llvm-svn: 40549
2007-07-27 12:58:54 +00:00
Dan Gohman
0fc4e0cf47 Don't ignore the return value of AsmPrinter::doInitialization and
AsmPrinter::doFinalization.

llvm-svn: 40487
2007-07-25 19:33:14 +00:00
Evan Cheng
53cb03b583 No more noResults.
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng
cdb4e7949f Added -print-emitted-asm to print out JIT generated asm to cerr.
llvm-svn: 40123
2007-07-20 21:56:13 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Evan Cheng
45eb268032 Only adjust esp around calls in presence of alloca.
llvm-svn: 40030
2007-07-19 00:42:58 +00:00
Chris Lattner
71e2481181 no email addrs in file headers
llvm-svn: 39962
2007-07-17 05:56:43 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
2007-07-14 14:06:15 +00:00
Dale Johannesen
eb2c2823e3 ARM: make branch folder remove unconditional branches
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782
2007-07-12 16:45:35 +00:00
Dale Johannesen
cacc6dbeb6 Fix hang compiling TimberWolf (allow for islands
of size other than 4).

llvm-svn: 39743
2007-07-11 18:32:38 +00:00
Evan Cheng
f6d010e93d Didn't mean the last commit. Revert.
llvm-svn: 38515
2007-07-10 22:00:16 +00:00
Evan Cheng
05c784cc30 Update.
llvm-svn: 38513
2007-07-10 21:49:47 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Chris Lattner
4810c53b05 The various "getModuleMatchQuality" implementations should return
zero if they see a target triple they don't understand.

llvm-svn: 38463
2007-07-09 17:25:29 +00:00
Evan Cheng
d9d3be078c No need for ccop anymore.
llvm-svn: 37965
2007-07-06 23:34:09 +00:00
Evan Cheng
92e624a6f7 Incorrect check.
llvm-svn: 37962
2007-07-06 23:23:19 +00:00
Evan Cheng
3b1b3eba6a Do away with ImmutablePredicateOperand.
llvm-svn: 37961
2007-07-06 23:22:46 +00:00
Evan Cheng
721b83bbe6 Print the s bit if the instruction is toggled to its CPSR setting form.
llvm-svn: 37932
2007-07-06 01:01:34 +00:00
Evan Cheng
c2c0b495ed PredicateDefOperand -> OptionalDefOperand.
llvm-svn: 37931
2007-07-06 01:00:49 +00:00
Evan Cheng
96254545ae Initial ARM JIT support by Raul Fernandes Herbster.
llvm-svn: 37926
2007-07-05 21:15:40 +00:00
Evan Cheng
a59422068f Unbreak the build.
llvm-svn: 37914
2007-07-05 17:13:19 +00:00
Gabor Greif
5f705671e4 Here is the bulk of the sanitizing.
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
2007-07-05 17:07:56 +00:00
Evan Cheng
be54fdf431 Reflects the chanegs made to PredicateOperand.
llvm-svn: 37898
2007-07-05 07:18:20 +00:00
Evan Cheng
3d2cfd8bb1 Added ARM::CPSR to represent ARM CPSR status register.
llvm-svn: 37897
2007-07-05 07:17:13 +00:00
Evan Cheng
2403cc41ea Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
llvm-svn: 37896
2007-07-05 07:15:27 +00:00
Evan Cheng
ef8a1bcbc3 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
llvm-svn: 37895
2007-07-05 07:13:32 +00:00
Evan Cheng
4af116139b Added ARM::CPSR to represent ARM CPSR status register.
llvm-svn: 37894
2007-07-05 07:11:03 +00:00
John Criswell
57e5ed4b5a Convert .cvsignore files
llvm-svn: 37801
2007-06-29 16:35:07 +00:00
Evan Cheng
5506831e5b Silence a warning.
llvm-svn: 37737
2007-06-26 18:31:22 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Owen Anderson
89558a0db6 Fix the build.
llvm-svn: 37705
2007-06-22 16:59:54 +00:00
Dan Gohman
a62327ea40 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
2007-06-22 14:59:07 +00:00
Dale Johannesen
e1c767df50 Quote complex names for Darwin X86 and ARM.
llvm-svn: 37700
2007-06-22 00:54:56 +00:00
Evan Cheng
5da7b6f0fc Be more conservative of duplicating blocks.
llvm-svn: 37669
2007-06-19 23:55:02 +00:00
Evan Cheng
c49382e48f Allow predicated immediate ARM to ARM calls.
llvm-svn: 37659
2007-06-19 21:05:09 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00