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8407076508
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439 Commits

Author SHA1 Message Date
Matt Arsenault
8407076508 R600/SI: Use bcnt instruction for ctpop 
llvm-svn: 210567
 2014-06-10 19:18:21 +00:00
Matt Arsenault
d30b483e1a R600: Handle fcopysign 
llvm-svn: 210564
 2014-06-10 19:00:20 +00:00
Matt Arsenault
5bfef73e00 R600/SI: Handle sign_extend and zero_extend to i64 with patterns. 
llvm-svn: 210563
 2014-06-10 18:54:59 +00:00
Tom Stellard
aab1db4cd9 SelectionDAG: Expand SELECT_CC to SELECT + SETCC 
This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

llvm-svn: 210539
 2014-06-10 16:01:22 +00:00
Alp Toker
03b6e12fae Reduce verbiage of lit.local.cfg files 
We can just split targets_to_build in one place and make it immutable.

llvm-svn: 210496
 2014-06-09 22:42:55 +00:00
Matt Arsenault
c9f3bd4d6c R600/SI: Keep 64-bit not on SALU 
llvm-svn: 210476
 2014-06-09 16:36:31 +00:00
Matt Arsenault
a34a3c834c R600: Fix selection failure for vector bswap 
llvm-svn: 210475
 2014-06-09 16:20:25 +00:00
Matt Arsenault
232bf82e54 R600: Add more and testcases 
llvm-svn: 210453
 2014-06-09 08:36:53 +00:00
Rafael Espindola
e5f71f18e0 Allow aliases to be unnamed_addr. 
Alias with unnamed_addr were in a strange state. It is stored in GlobalValue,
the language reference talks about "unnamed_addr aliases" but the verifier
was rejecting them.

It seems natural to allow unnamed_addr in aliases:

* It is a property of how it is accessed, not of the data itself.
* It is perfectly possible to write code that depends on the address
of an alias.

This patch then makes unname_addr legal for aliases. One side effect is that
the syntax changes for a corner case: In globals, unnamed_addr is now printed
before the address space.

llvm-svn: 210302
 2014-06-06 01:20:28 +00:00
Matt Arsenault
700a8a731b R600: Fix test. Using wrong check prefix. 
llvm-svn: 210244
 2014-06-05 08:00:36 +00:00
Matt Arsenault
9e400b2e26 R600/SI: Match rsq instructions 
llvm-svn: 210226
 2014-06-05 00:15:55 +00:00
Matt Arsenault
ff3cea9ab5 R600/SI: Fix [s|u]int_to_fp for i1 
llvm-svn: 209971
 2014-05-31 06:47:42 +00:00
Matt Arsenault
bfc007dbb5 R600: Try to convert BFE back to standard bit ops when possible. 
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

llvm-svn: 209462
 2014-05-22 18:09:12 +00:00
Matt Arsenault
90d0fd2ea0 R600: Add dag combine for BFE 
llvm-svn: 209461
 2014-05-22 18:09:07 +00:00
Matt Arsenault
4ab9246e99 R600: Implement ComputeNumSignBitsForTargetNode for BFE 
llvm-svn: 209460
 2014-05-22 18:09:03 +00:00
Matt Arsenault
c7d0679684 R600: Expand mul24 for GPUs without it 
llvm-svn: 209458
 2014-05-22 18:00:24 +00:00
Matt Arsenault
fcb6cf68ee R600: Expand mad24 for GPUs without it 
llvm-svn: 209457
 2014-05-22 18:00:20 +00:00
Matt Arsenault
e43426533f R600: Add intrinsics for mad24 
llvm-svn: 209456
 2014-05-22 18:00:15 +00:00
Matt Arsenault
cec6ae49e8 R600/SI: Match fp_to_uint / uint_to_fp for f64 
llvm-svn: 209388
 2014-05-22 03:20:30 +00:00
Matt Arsenault
094f9f1e9c R600: Partially fix constant initializers for structs and vectors. 
This should extend the current workaround to work with structs
that only contain legal, scalar types.

llvm-svn: 209331
 2014-05-21 22:42:42 +00:00
Matt Arsenault
dc960fcadc R600: Add failing testcases for constant initializers. 
Constant initializers involving illegal types hit an assertion.

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

llvm-svn: 209330
 2014-05-21 22:42:38 +00:00
Tom Stellard
2022c1eb1b R600/SI: Promote f32 SELECT to i32 
llvm-svn: 209024
 2014-05-16 20:56:41 +00:00
Tom Stellard
77051e93a5 R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0 
llvm-svn: 208886
 2014-05-15 14:41:54 +00:00
Tom Stellard
efb8470c62 R600/SI: Use VALU instructions for i1 ops 
llvm-svn: 208885
 2014-05-15 14:41:50 +00:00
Jay Foad
e0eac700cb Rename ComputeMaskedBits to computeKnownBits. "Masked" has been 
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
 2014-05-14 21:14:37 +00:00
Matt Arsenault
102b7be363 R600/SI: Try to fix BFE operands when moving to VALU 
This was broken by r208479

llvm-svn: 208740
 2014-05-13 23:45:50 +00:00
Matt Arsenault
c2251d492b R600: Add mul24 intrinsics 
llvm-svn: 208604
 2014-05-12 17:49:57 +00:00
Matt Arsenault
43171f4aad Make SimplifyDemandedBits understand BUILD_PAIR 
llvm-svn: 208598
 2014-05-12 17:14:48 +00:00
Vincent Lejeune
03352d8b38 R600/SI: Fold fabs/fneg into src input modifier 
llvm-svn: 208480
 2014-05-10 19:18:39 +00:00
Vincent Lejeune
840594f1e6 R600/SI: Prettier display of input modifiers 
llvm-svn: 208479
 2014-05-10 19:18:33 +00:00
Tom Stellard
1a986ede50 R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructions 
llvm-svn: 208432
 2014-05-09 16:42:22 +00:00
Tom Stellard
550d79da42 R600/SI: Fix SMRD pattern for offsets > 32 bits 
We were dropping the high bits of 64-bit immediate offsets.

llvm-svn: 208431
 2014-05-09 16:42:21 +00:00
Tom Stellard
9562e8a6ba R600: Expand i64 SELECT_CC 
llvm-svn: 208430
 2014-05-09 16:42:19 +00:00
Tom Stellard
83d3208148 R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine() 
llvm-svn: 208429
 2014-05-09 16:42:16 +00:00
Tom Stellard
1291d8f8c2 R600: Expand i64 ISD:SUB 
llvm-svn: 208005
 2014-05-05 21:47:15 +00:00
Tom Stellard
18ca382db4 R600: Expand vector sin and cos. 
v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 207845
 2014-05-02 15:41:47 +00:00
Tom Stellard
05e86018ff R600: Expand TruncStore i64 -> {i16,i8} 
llvm-svn: 207844
 2014-05-02 15:41:46 +00:00
Matt Arsenault
293918660a R600/SI: Fix verifier error with pseudo store instructions. 
Use i32 instead of specifying SReg_32. When this is
the pseudo INDIRECT_BASE_ADDR, this would give a bogus
verifier error.

llvm-svn: 207770
 2014-05-01 16:37:52 +00:00
Tom Stellard
690d34daa4 R600/SI: Use VALU instructions for copying i1 values 
We can't use SALU instructions for this since they ignore the EXEC mask
and are always executed.

This fixes several OpenCV tests.

llvm-svn: 207661
 2014-04-30 15:31:33 +00:00
Tom Stellard
5a08396499 R600/SI: Teach moveToVALU how to handle some SMRD instructions 
llvm-svn: 207660
 2014-04-30 15:31:29 +00:00
Tom Stellard
c58951c37c R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors 
SI_IF and SI_ELSE are terminators which also produce a value.  For
these instructions ISel always inserts a COPY to move their value
to another basic block.  This COPY ends up between SI_(IF|ELSE)
and the S_BRANCH* instruction at the end of the block.

This breaks MachineBasicBlock::getFirstTerminator() and also the
machine verifier which assumes that terminators are grouped together at
the end of blocks.

To solve this we coalesce the copy away right after ISel to make sure
there are no instructions in between terminators at the end of blocks.

llvm-svn: 207591
 2014-04-29 23:12:53 +00:00
Tom Stellard
26a1c5b403 R600/SI: Only select SALU instructions in the entry or exit block 
SALU instructions ignore control flow, so it is not always safe to use
them within branches.  This is a partial solution to this problem
until we can come up with something better.

llvm-svn: 207590
 2014-04-29 23:12:48 +00:00
Tom Stellard
9112e301ba R600: optimize the UDIVREM 64 algorithm 
This is a squash of several optimization commits:
 - calculate DIV_Lo and DIV_Hi separately
 - use BFE_U32 if we are operating on 32bit values
 - use precomputed constants instead of shifting in UDVIREM
 - skip the first 32 iterations of udivrem

v2: Check whether BFE is supported before using it

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 207589
 2014-04-29 23:12:46 +00:00
Matt Arsenault
e34c30a3c0 R600: Add a test that used to be broken that I forgot to add 
llvm-svn: 207017
 2014-04-23 19:45:05 +00:00
Matt Arsenault
f022fe68e4 R600: Emit error instead of unreachable on function call 
llvm-svn: 206904
 2014-04-22 16:42:00 +00:00
Matt Arsenault
01a0b32658 R600: Make sign_extend_inreg legal. 
Don't know why I didn't just do this in the first place.

llvm-svn: 206862
 2014-04-22 03:49:30 +00:00
Matt Arsenault
6b6f53eaec R600/SI: Try to use scalar BFE. 
Use scalar BFE with constant shift and offset when possible.
This is complicated by the fact that the scalar version packs
the two operands of the vector version into one.

llvm-svn: 206558
 2014-04-18 05:19:26 +00:00
Matt Arsenault
42cf57d738 R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16 
llvm-svn: 206547
 2014-04-18 01:53:18 +00:00
Tom Stellard
59f91bb185 R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR 
llvm-svn: 206541
 2014-04-18 00:36:21 +00:00
Tom Stellard
50135a875d R600/SI: Stop using i128 as the resource descriptor type 
Having i128 as a legal type complicates the legalization phase.  v4i32
is already a legal type, so we will use that instead.

This fixes several piglit tests.

llvm-svn: 206500
 2014-04-17 21:00:11 +00:00